From: Archit Taneja <architt@codeaurora.org>
To: Stephen Boyd <sboyd@codeaurora.org>
Cc: mturquette@linaro.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: qcom: fix RCG M/N counter configuration
Date: Fri, 20 Mar 2015 11:42:02 +0530 [thread overview]
Message-ID: <550BBA32.8060308@codeaurora.org> (raw)
In-Reply-To: <20150320052807.GA11451@codeaurora.org>
On 03/20/2015 10:58 AM, Stephen Boyd wrote:
> On 03/04, Archit Taneja wrote:
>> Currently, a RCG's M/N counter (used for fraction division) is set to either
>> 'bypass' (counter disabled) or 'dual edge' (counter enabled) based on whether
>> the corresponding rcg struct has a mnd field specified and a non-zero N.
>>
>> In the case where M and N are the same value, the M/N counter is still enabled
>> by code even though no division takes place. Leaving the RCG in such a state
>> can result in improper behavior. This was observed with the DSI pixel clock RCG
>> when M and N were both set to 1.
>>
>> Add an additional check (M != N) to enable the M/N counter only when it's needed
>> for fraction division.
>>
>> Signed-off-by: Archit Taneja <architt@codeaurora.org>
>> ---
>
> I'm going to queue this up for 4.1 given that this isn't a new
> regression. But I'll tag it for stable so that we get it into all
> the stable trees.
Great, that sounds good.
Thanks,
Archit
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
prev parent reply other threads:[~2015-03-20 6:12 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-04 9:49 [PATCH] clk: qcom: fix RCG M/N counter configuration Archit Taneja
2015-03-20 5:28 ` Stephen Boyd
2015-03-20 6:12 ` Archit Taneja [this message]
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