Re: [PATCH 07/12] xen: arm: Handle CP15 register traps from userspace

[Julien Grall <julien.grall@linaro.org>]

Hi Ian,

On 25/03/15 14:22, Ian Campbell wrote:
> Previously userspace access to PM* would have been incorrectly (but
> benignly) implemented as RAZ/WI when running on a 32-bit kernel and
> would cause a hypervisor exception (host crash) when running a 64-bit
> kernel (this was already solved via the fix to XSA-102).
> 
> CLIDR, CCSIDR, DCCISW, ACTLR, PMINTENSET, PMINTENCLR are EL1 only,
> attempts to access from EL0 will trap to EL1 not to us, hence BUG_ON
> is appropriate now.

For PMINTENSET and PMINTENCLR the spec (ARMv8 DDI0487A rev d) says:

"If MDCR_EL2.TPM==1, Non-secure accesses to this register will trap from
EL1 and EL0 to EL2."

As we set to 1 MDCR_EL1.TPM, EL0 access will trap to Xen. So I think we
should replace the BUG_ON to injected a exception.

Reading more the spec only ACTLR access from EL0 will trap to EL1. All
access from EL0 to the others registers in the list above will trap to EL2.

Although, the ARMv7 spec seems to say to only valid access will be trapped.

Regards,

-- 
Julien Grall