From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Cooper Subject: Re: [RFC v1 08/15] Update IRTE according to guest interrupt config changes Date: Fri, 27 Mar 2015 11:31:35 +0000 Message-ID: <55153F97.7020902@citrix.com> References: <1427286717-4093-1-git-send-email-feng.wu@intel.com> <1427286717-4093-9-git-send-email-feng.wu@intel.com> <55146507.4000707@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: "Wu, Feng" , "xen-devel@lists.xen.org" Cc: "Zhang, Yang Z" , "Tian, Kevin" , "keir@xen.org" , "JBeulich@suse.com" List-Id: xen-devel@lists.xenproject.org On 27/03/15 05:49, Wu, Feng wrote: >>> +/* >>> + * Here we handle the following cases: >>> + * - For lowest-priority interrupts, we find the destination vCPU from the >>> + * guest vector using vector-hashing mechamisn and return true. This >> follows >>> + * the hardware behavior, since modern Intel CPUs use vector hashing to >>> + * handle the lowest-priority interrupt. >> What is the hashing algorithm, or can I have some hint as to where to >> find it in a manual? > I asked hardware guys about this, there is no document about how hardware > implements the hashing algorithm. In which case you must carefully document the hashing algorithm in the comment. (And while you are at it, press for the hashing algorithm to find its way into an appropriate formal document.) ~Andrew