From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by yocto-www.yoctoproject.org (Postfix, from userid 118) id 20BC5E00922; Fri, 27 Mar 2015 07:25:24 -0700 (PDT) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on yocto-www.yoctoproject.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 X-Spam-HAM-Report: * -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high * trust * [135.245.210.21 listed in list.dnswl.org] * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] Received: from smtp-fr.alcatel-lucent.com (fr-hpida-esg-02.alcatel-lucent.com [135.245.210.21]) by yocto-www.yoctoproject.org (Postfix) with ESMTP id A8A16E00906 for ; Fri, 27 Mar 2015 07:25:19 -0700 (PDT) Received: from us70uusmtp4.zam.alcatel-lucent.com (unknown [135.5.2.66]) by Websense Email Security Gateway with ESMTPS id 5434FF7A2E567 for ; Fri, 27 Mar 2015 14:25:16 +0000 (GMT) Received: from umail.lucent.com (umail.ndc.lucent.com [135.3.40.61]) by us70uusmtp4.zam.alcatel-lucent.com (GMO) with ESMTP id t2REPHIR030505 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 27 Mar 2015 10:25:17 -0400 Received: from [135.222.138.133] (Ed-PC.mh.lucent.com [135.222.138.133]) by umail.lucent.com (8.13.8/TPES) with ESMTP id t2REPGv9015204 for ; Fri, 27 Mar 2015 09:25:16 -0500 (CDT) Message-ID: <5515682C.2010302@alcatel-lucent.com> Date: Fri, 27 Mar 2015 10:24:44 -0400 From: Ed Sutter User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 To: meta-freescale@yoctoproject.org References: <1427449171.3074.5.camel@perpic.it> <551555DA.7040901@alcatel-lucent.com> <1427465486.3074.10.camel@perpic.it> In-Reply-To: <1427465486.3074.10.camel@perpic.it> Subject: Re: IMX53 Custom board, ram... X-BeenThere: meta-freescale@yoctoproject.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Usage and development list for the meta-fsl-* layers List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Mar 2015 14:25:24 -0000 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit No problem... I found the file I changed. Note that this was part of u-boot-2013.10, so I don't know how much of this has changed since then. The change was in board/freescale/imx/ddr/mx6d_1x_mt41j128.cfg... DATA 4 0x021b0000 0x83180000 To change something in the MMDC. IIRC, this is a file that is preprocessed by uboot tools to become part of the initial image that is sucked in at initial bootload stages to configure the DDR. HTH, Ed > Thank you ED for your reply. > > Actually I'm in the prototyping phase. so actually I'm just thinking > about how much ram I will need and for cost optimization I need to think > off which part I can safely remove. > There's no hurry for that. After writing to the ML I found that in the > register ESDCTL that there's an option for setting the 16 bit. > I see that the register is used in this file: > http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/board/freescale/mx53_loco/flash_header.S?h=imx_v2009.08 > > so ideally if I set: REG_LD_AND_STR_OP(31, 0x000, 0xc3190000) to > REG_LD_AND_STR_OP(31, 0x000, 0xc3180000) > > I should be able to set the micro DDR interface to 16 bit mode. > > Only if you remember that. Looks this one a solution like the one you > did? > > Thank you > Andrea > > Il giorno ven, 27/03/2015 alle 14.06 +0100, Ed Sutter ha scritto: >> Andrea, >> A while back the first spin of our iMX6 based board had a bug that >> messed up the upper >> 16 bits or our 32-bit DRAM interface. I was able to temporarily run >> this as a single bank >> in 16 bit mode. This was not with yocto however. I would have to dig a >> bit to recall what I >> had to change (I don't think it was the file you're pointing to); let me >> know if you >> need that. >> Ed >>> Hello everybody, >>> >>> I would like to know what is the minimum requirement of ram that I need >>> to put on the board. >>> I saw for example that I can use MT41K128M16JT-125 XIT from Micron. >>> it looks like it is a 16 bit ram. >>> I know that for a project the ram usage is really low. It is a 16bit >>> ddr3. I didn't understand if I can use only 1 ram bank or if I need to >>> use (at least 2). On IMX53qsb there's 4 banks but reading: >>> http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/include/configs/mx53_loco.h?h=imx_v2009.08 >>> it looks like that I can define CONFIG_NR_DRAM_BANKS to 1. 1 bank of >>> 32bit? or I can use 1 bank of 16bit? >>> >>> Thank you for the reading >>> Andrea >> >> -- >> Ed Sutter >> Alcatel-Lucent Technologies -- Bell Laboratories >> Phone: 908-582-2351 >> Email: ed.sutter@alcatel-lucent.com >> -- Ed Sutter Alcatel-Lucent Technologies -- Bell Laboratories Phone: 908-582-2351 Email: ed.sutter@alcatel-lucent.com