From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH v4 08/15] xen: arm: don't pretend to handle cache maintenance by set/way Date: Fri, 27 Mar 2015 16:36:28 +0000 Message-ID: <5515870C.1080702@linaro.org> References: <1427466798.13935.158.camel@citrix.com> <1427466824-31967-8-git-send-email-ian.campbell@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1427466824-31967-8-git-send-email-ian.campbell@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell , xen-devel@lists.xen.org Cc: tim@xen.org, stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org Hi Ian, On 27/03/15 14:33, Ian Campbell wrote: > We set HCR_EL2.TSW but only (sort of) handle 32-bit access to DCCISW > but not the other two registers, nor any 64-bit access. Add handlers > for all of these. We don't set HCR_EL2.TSW so DCCISW is not trapped. > diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h > index c2dcb66..cf3d6cc 100644 > --- a/xen/include/public/arch-arm.h > +++ b/xen/include/public/arch-arm.h > @@ -161,6 +161,11 @@ > * > * - The device tree Xen compatible node is fully described under Linux > * at Documentation/devicetree/bindings/arm/xen.txt. > + * > + * - Cache maintenaince operations by set/way ("dc isw|cisw|csw" and > + * the equivalent cp15 registers) are not available when running > + * under Xen and will result in an undefined instruction exception > + * delivered to the guest. > */ set/way operations is used by Linux ARM32 in order to flush all the cache. Injecting an undefined instruction would make guest unusable. Regards, -- Julien Grall