From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH v4 09/15] xen: arm: Handle CP15 register traps from userspace Date: Fri, 27 Mar 2015 16:39:13 +0000 Message-ID: <551587B1.3060505@linaro.org> References: <1427466798.13935.158.camel@citrix.com> <1427466824-31967-9-git-send-email-ian.campbell@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1427466824-31967-9-git-send-email-ian.campbell@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell , xen-devel@lists.xen.org Cc: tim@xen.org, stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org Hi Ian, On 27/03/15 14:33, Ian Campbell wrote: > Previously userspace access to PM* would have been incorrectly (but > benignly) implemented as RAZ/WI when running on a 32-bit kernel and > would cause a hypervisor exception (host crash) when running a 64-bit > kernel (this was already solved via the fix to XSA-102). > > PMINTENSET, PMINTENCLR are EL1 only, but it is not clear whether > attempts to access from EL0 will trap to EL1 or EL2, be conservative > and handle EL0 access with an undef injection. > > ACTLR is EL1 only and the ARM ARM states that HCR_EL2.TACR causes > accesses from EL1 to trap. However remain conservative even here and > handle accesses from EL0 by injecting an undef injection. > > PMUSERENR is R/O at EL0 and we implement as RAZ/WI at EL1 as before. > > The remaining PM* registers are accessible to EL0 only if > PMUSERENR_EL0.EN is set, since we emulate this as RAZ/WI the bit is > never set so we inject a trap on attempted access. We weren't > previously handling PMCCNTR. > > HSR_EC_CP15_32 should never be seen from a 64-bit guest, so BUG_ON if > that occurs. > > Signed-off-by: Ian Campbell Reviewed-by: Julien Grall Regards, -- Julien Grall