From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH v4 11/15] xen: arm: correctly handle sysreg accesses from userspace Date: Fri, 27 Mar 2015 16:40:04 +0000 Message-ID: <551587E4.2090409@linaro.org> References: <1427466798.13935.158.camel@citrix.com> <1427466824-31967-11-git-send-email-ian.campbell@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1427466824-31967-11-git-send-email-ian.campbell@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell , xen-devel@lists.xen.org Cc: tim@xen.org, stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org Hi Ian, On 27/03/15 14:33, Ian Campbell wrote: > Previously we implemented all registers as RAZ/WI even if they > shouldn't be accessible to userspace. > > It is not entirely clear whether attempts to access *_EL1 registers > from EL0 will trap to EL1 or EL2, be conservative and treat as an > undef injection. > > PMUSERENR_EL0 and MDCCSR_EL0 are R/O to EL0. MDCCSR_EL0 was previously > not handled at all. > > Other PM*_EL0 registers are accessible at EL0 only if PMUSERENR_EL0.EN > is set, since we emulate that as RAZ/WI we know that bit cannot be > set. > > Signed-off-by: Ian Campbell Reviewed-by: Julien Grall Regards, -- Julien Grall