* Re: Fwd: Ask for help: ARM: mvebu: add NAND support for dove [not found] ` <551714F8.2050401@gmail.com> @ 2015-03-29 10:20 ` Sebastian Hesselbarth 2015-03-29 23:34 ` Ezequiel Garcia 1 sibling, 0 replies; 6+ messages in thread From: Sebastian Hesselbarth @ 2015-03-29 10:20 UTC (permalink / raw) To: Gabriel Dobato Cc: Jean-Francois Moine, ezequiel.garcia, mt >> linux-mtd@lists.infradead.org, Ezequiel Garcia, linux-arm-kernel On 28.03.2015 21:54, Gabriel Dobato wrote: > I am trying to set the Nand in a CM-510 Compulab based board (4.0-rc5). > > As pxa3xx-nand driver supports NFCv1 (PXA3xx) and NFCv2 (Armada 370/XP), > I think that it should work more or less with Dove SoC (NFCv1) that is > similar enough. Gabriel, I haven't compared Dove NFC with the one from PXA3xx or Armada 370/XP in detail, yet. I doubt that it will be fully compatible with Armada 370/XP as you state it is NFCv2 above. > Until now, I've only added the correspondent node in dove.dtsi and the > partitions in dove-cm-a510.dts ( it should be updated in the patch > series that Sebastian Hesselbarth submitted ) : We'll deal with it as soon as the i2c-mux thing is worked out. > --- > arch/arm/boot/dts/dove-cm-a510.dts | 17 +++++++++++++++++ > arch/arm/boot/dts/dove.dtsi | 16 ++++++++++++++++ > 2 files changed, 33 insertions(+) > > diff --git a/arch/arm/boot/dts/dove-cm-a510.dts > b/arch/arm/boot/dts/dove-cm-a510.dts > index 50c0d69..36cf10d 100644 > --- a/arch/arm/boot/dts/dove-cm-a510.dts > +++ b/arch/arm/boot/dts/dove-cm-a510.dts > @@ -36,3 +36,20 @@ > &i2c0 { > status = "okay"; > }; > + > +&nand { > + status = "okay"; > + num-cs = <1>; > + partition@0 { > + label = "uImage"; > + reg = <0x000000000000 0x000000400000>; #address-cells and #size-cells of &nand below is <1> each, so above should be 32b values. If it would be 64b it would have to be split into two 32b values anyway. > + }; > + partition@400000 { > + label = "Rootfs"; > + reg = <0x000000400000 0x00001FC00000>; > + }; > +}; > + > + > + > + Please avoid adding extra whitespaces. > diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi > index a5441d5..7e71f45 100644 > --- a/arch/arm/boot/dts/dove.dtsi > +++ b/arch/arm/boot/dts/dove.dtsi > @@ -380,6 +380,22 @@ > status = "disabled"; > }; > > + nand: nand@c0000 { > + compatible = "marvell,armada370-nand"; As said above, I doubt Dove NFC is fully compatible with Armada 370 NFC. Ezequiel can tell for sure, as he probably knows Marvell NFC best. > + #address-cells = <1>; > + #size-cells = <1>; > + reg= <0xc0000 0x60>; > + interrupts = <3>; > + clocks = <&core_clk 0>; There is a clock gate for NFC, check Dove FS, Clock Gating Control register, bit 10. Above should be: clocks = <&gate_clk 10>; > + pinctrl-0 = <&pmx_nand>; > + pinctrl-names = "default"; > + marvell,nand-keep-config; > + marvell,nand-enable-arbiter; I haven't checked the foo-arbiter property, but are you sure it is available on Dove? Sebastian > + nand-on-flash-bbt; > + }; > + > + > + > thermal: thermal-diode@d001c { > compatible = "marvell,dove-thermal"; > reg = <0xd001c 0x0c>, <0xd005c 0x08>; ^ permalink raw reply [flat|nested] 6+ messages in thread
* Fwd: Ask for help: ARM: mvebu: add NAND support for dove @ 2015-03-29 10:20 ` Sebastian Hesselbarth 0 siblings, 0 replies; 6+ messages in thread From: Sebastian Hesselbarth @ 2015-03-29 10:20 UTC (permalink / raw) To: linux-arm-kernel On 28.03.2015 21:54, Gabriel Dobato wrote: > I am trying to set the Nand in a CM-510 Compulab based board (4.0-rc5). > > As pxa3xx-nand driver supports NFCv1 (PXA3xx) and NFCv2 (Armada 370/XP), > I think that it should work more or less with Dove SoC (NFCv1) that is > similar enough. Gabriel, I haven't compared Dove NFC with the one from PXA3xx or Armada 370/XP in detail, yet. I doubt that it will be fully compatible with Armada 370/XP as you state it is NFCv2 above. > Until now, I've only added the correspondent node in dove.dtsi and the > partitions in dove-cm-a510.dts ( it should be updated in the patch > series that Sebastian Hesselbarth submitted ) : We'll deal with it as soon as the i2c-mux thing is worked out. > --- > arch/arm/boot/dts/dove-cm-a510.dts | 17 +++++++++++++++++ > arch/arm/boot/dts/dove.dtsi | 16 ++++++++++++++++ > 2 files changed, 33 insertions(+) > > diff --git a/arch/arm/boot/dts/dove-cm-a510.dts > b/arch/arm/boot/dts/dove-cm-a510.dts > index 50c0d69..36cf10d 100644 > --- a/arch/arm/boot/dts/dove-cm-a510.dts > +++ b/arch/arm/boot/dts/dove-cm-a510.dts > @@ -36,3 +36,20 @@ > &i2c0 { > status = "okay"; > }; > + > +&nand { > + status = "okay"; > + num-cs = <1>; > + partition at 0 { > + label = "uImage"; > + reg = <0x000000000000 0x000000400000>; #address-cells and #size-cells of &nand below is <1> each, so above should be 32b values. If it would be 64b it would have to be split into two 32b values anyway. > + }; > + partition at 400000 { > + label = "Rootfs"; > + reg = <0x000000400000 0x00001FC00000>; > + }; > +}; > + > + > + > + Please avoid adding extra whitespaces. > diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi > index a5441d5..7e71f45 100644 > --- a/arch/arm/boot/dts/dove.dtsi > +++ b/arch/arm/boot/dts/dove.dtsi > @@ -380,6 +380,22 @@ > status = "disabled"; > }; > > + nand: nand at c0000 { > + compatible = "marvell,armada370-nand"; As said above, I doubt Dove NFC is fully compatible with Armada 370 NFC. Ezequiel can tell for sure, as he probably knows Marvell NFC best. > + #address-cells = <1>; > + #size-cells = <1>; > + reg= <0xc0000 0x60>; > + interrupts = <3>; > + clocks = <&core_clk 0>; There is a clock gate for NFC, check Dove FS, Clock Gating Control register, bit 10. Above should be: clocks = <&gate_clk 10>; > + pinctrl-0 = <&pmx_nand>; > + pinctrl-names = "default"; > + marvell,nand-keep-config; > + marvell,nand-enable-arbiter; I haven't checked the foo-arbiter property, but are you sure it is available on Dove? Sebastian > + nand-on-flash-bbt; > + }; > + > + > + > thermal: thermal-diode at d001c { > compatible = "marvell,dove-thermal"; > reg = <0xd001c 0x0c>, <0xd005c 0x08>; ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Fwd: Ask for help: ARM: mvebu: add NAND support for dove [not found] ` <551714F8.2050401@gmail.com> @ 2015-03-29 23:34 ` Ezequiel Garcia 2015-03-29 23:34 ` Ezequiel Garcia 1 sibling, 0 replies; 6+ messages in thread From: Ezequiel Garcia @ 2015-03-29 23:34 UTC (permalink / raw) To: Gabriel Dobato, linux-arm-kernel, mt >> linux-mtd@lists.infradead.org Cc: Jean-Francois Moine, ezequiel.garcia, Sebastian Hesselbarth On 03/28/2015 05:54 PM, Gabriel Dobato wrote: [..] > However, if I try to read/write into the mtd partitions, I can not, > there are errors: > > root@debug:~# nandwrite -p /dev/mtd0 /uImage > Writing at 0x00000000 > pxa3xx-nand f10c0000.nand: Wait time out!!! > > root@debug:~# flash_erase /dev/mtd0 0 0 > Erasing 128 Kibyte @ 0 -- 0 % complete pxa3xx-nand f10c0000.nand: Wait > time out!!! > > root@debug:~# cat /dev/mtd0 > pxa3xx-nand f10c0000.nand: Wait time out!!! > Maybe a silly question, but does your bootloader initializes the controller? Are you able to read/write/erase using it? The current pxa3xx-nand driver relies on that for Armada370/XP, as timing setup is not properly handled. -- Ezequiel Garcia, VanguardiaSur www.vanguardiasur.com.ar ^ permalink raw reply [flat|nested] 6+ messages in thread
* Fwd: Ask for help: ARM: mvebu: add NAND support for dove @ 2015-03-29 23:34 ` Ezequiel Garcia 0 siblings, 0 replies; 6+ messages in thread From: Ezequiel Garcia @ 2015-03-29 23:34 UTC (permalink / raw) To: linux-arm-kernel On 03/28/2015 05:54 PM, Gabriel Dobato wrote: [..] > However, if I try to read/write into the mtd partitions, I can not, > there are errors: > > root at debug:~# nandwrite -p /dev/mtd0 /uImage > Writing at 0x00000000 > pxa3xx-nand f10c0000.nand: Wait time out!!! > > root at debug:~# flash_erase /dev/mtd0 0 0 > Erasing 128 Kibyte @ 0 -- 0 % complete pxa3xx-nand f10c0000.nand: Wait > time out!!! > > root at debug:~# cat /dev/mtd0 > pxa3xx-nand f10c0000.nand: Wait time out!!! > Maybe a silly question, but does your bootloader initializes the controller? Are you able to read/write/erase using it? The current pxa3xx-nand driver relies on that for Armada370/XP, as timing setup is not properly handled. -- Ezequiel Garcia, VanguardiaSur www.vanguardiasur.com.ar ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Fwd: Ask for help: ARM: mvebu: add NAND support for dove 2015-03-29 23:34 ` Ezequiel Garcia @ 2015-03-30 7:01 ` Gabriel Dobato -1 siblings, 0 replies; 6+ messages in thread From: Gabriel Dobato @ 2015-03-30 7:01 UTC (permalink / raw) To: Ezequiel Garcia, Sebastian Hesselbarth Cc: Jean-Francois Moine, mt >> linux-mtd@lists.infradead.org, ezequiel.garcia, linux-arm-kernel Sebastian, > #address-cells and #size-cells of &nand below is <1> each, so above > should be 32b values. If it would be 64b it would have to be split > into two 32b values anyway. Yes, you are right. I have to change it. > As said above, I doubt Dove NFC is fully compatible with Armada 370 NFC. > Ezequiel can tell for sure, as he probably knows Marvell NFC best. I am not sure, that's why I am asking for help. Looking at Specification, they seem to be similar enough. Ezequiel told me that pxa3xx-nand driver should be more or less compatible (using "marvell,armada370-nand" string for the compatible property). > > There is a clock gate for NFC, check Dove FS, Clock Gating Control > register, bit 10. Above should be: > > clocks = <&gate_clk 10>; As always, you found it. After changing it : root@debug:~# flash_eraseall /dev/mtd0 flash_eraseall has been replaced by `flash_erase <mtddev> 0 0`; please use it Erasing 128 Kibyte @ 1fee0000 -- 99 % complete flash_erase: Skipping bad block at 1ff00000 flash_erase: Skipping bad block at 1ff20000 flash_erase: Skipping bad block at 1ff40000 flash_erase: Skipping bad block at 1ff60000 flash_erase: Skipping bad block at 1ff80000 flash_erase: Skipping bad block at 1ffa0000 flash_erase: Skipping bad block at 1ffc0000 flash_erase: Skipping bad block at 1ffe0000 Erasing 128 Kibyte @ 1ffe0000 -- 100 % complete root@debug:~# nandwrite -p /dev/mtd0 /uImage Writing data to block 0 at offset 0x0 Writing data to block 1 at offset 0x20000 Writing data to block 2 at offset 0x40000 Writing data to block 3 at offset 0x60000 Writing data to block 4 at offset 0x80000 Writing data to block 5 at offset 0xa0000 Writing data to block 6 at offset 0xc0000 Writing data to block 7 at offset 0xe0000 Writing data to block 8 at offset 0x100000 Writing data to block 9 at offset 0x120000 Writing data to block 10 at offset 0x140000 Writing data to block 11 at offset 0x160000 Writing data to block 12 at offset 0x180000 Writing data to block 13 at offset 0x1a0000 Writing data to block 14 at offset 0x1c0000 Writing data to block 15 at offset 0x1e0000 Writing data to block 16 at offset 0x200000 Writing data to block 17 at offset 0x220000 Writing data to block 18 at offset 0x240000 Writing data to block 19 at offset 0x260000 Writing data to block 20 at offset 0x280000 Writing data to block 21 at offset 0x2a0000 Writing data to block 22 at offset 0x2c0000 Writing data to block 23 at offset 0x2e0000 Writing data to block 24 at offset 0x300000 Writing data to block 25 at offset 0x320000 Writing data to block 26 at offset 0x340000 Writing data to block 27 at offset 0x360000 root@debug:~# CM-A510>> nboot 200000 nand0 0 no partition number specified Loading from nand0, offset 0x0 Bad block table found at page 262080, version 0x01 Bad block table found at page 262016, version 0x01 Image Name: Linux kernel Created: 2015-03-30 6:41:19 UTC Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 3637235 Bytes = 3.5 MB Load Address: 00008000 Entry Point: 00008000 CM-A510>> bootm ## Booting kernel from Legacy Image at 00200000 ... Image Name: Linux kernel Created: 2015-03-30 6:41:19 UTC Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 3637235 Bytes = 3.5 MB Load Address: 00008000 Entry Point: 00008000 Verifying Checksum ... OK Loading Kernel Image ... OK OK Starting kernel ... Booting Linux on physical CPU 0x0 ... > On 30/03/15 01:34, Ezequiel Garcia wrote: >> Maybe a silly question, but does your bootloader initializes the >> controller? Are you able to read/write/erase using it? >> >> The current pxa3xx-nand driver relies on that for Armada370/XP, as >> timing setup is not properly handled. Ezequiel, Yes, it initializes the controller. Gabriel Dobato ^ permalink raw reply [flat|nested] 6+ messages in thread
* Fwd: Ask for help: ARM: mvebu: add NAND support for dove @ 2015-03-30 7:01 ` Gabriel Dobato 0 siblings, 0 replies; 6+ messages in thread From: Gabriel Dobato @ 2015-03-30 7:01 UTC (permalink / raw) To: linux-arm-kernel Sebastian, > #address-cells and #size-cells of &nand below is <1> each, so above > should be 32b values. If it would be 64b it would have to be split > into two 32b values anyway. Yes, you are right. I have to change it. > As said above, I doubt Dove NFC is fully compatible with Armada 370 NFC. > Ezequiel can tell for sure, as he probably knows Marvell NFC best. I am not sure, that's why I am asking for help. Looking at Specification, they seem to be similar enough. Ezequiel told me that pxa3xx-nand driver should be more or less compatible (using "marvell,armada370-nand" string for the compatible property). > > There is a clock gate for NFC, check Dove FS, Clock Gating Control > register, bit 10. Above should be: > > clocks = <&gate_clk 10>; As always, you found it. After changing it : root at debug:~# flash_eraseall /dev/mtd0 flash_eraseall has been replaced by `flash_erase <mtddev> 0 0`; please use it Erasing 128 Kibyte @ 1fee0000 -- 99 % complete flash_erase: Skipping bad block at 1ff00000 flash_erase: Skipping bad block at 1ff20000 flash_erase: Skipping bad block at 1ff40000 flash_erase: Skipping bad block at 1ff60000 flash_erase: Skipping bad block at 1ff80000 flash_erase: Skipping bad block at 1ffa0000 flash_erase: Skipping bad block at 1ffc0000 flash_erase: Skipping bad block at 1ffe0000 Erasing 128 Kibyte @ 1ffe0000 -- 100 % complete root at debug:~# nandwrite -p /dev/mtd0 /uImage Writing data to block 0 at offset 0x0 Writing data to block 1 at offset 0x20000 Writing data to block 2 at offset 0x40000 Writing data to block 3 at offset 0x60000 Writing data to block 4 at offset 0x80000 Writing data to block 5 at offset 0xa0000 Writing data to block 6 at offset 0xc0000 Writing data to block 7 at offset 0xe0000 Writing data to block 8 at offset 0x100000 Writing data to block 9 at offset 0x120000 Writing data to block 10 at offset 0x140000 Writing data to block 11 at offset 0x160000 Writing data to block 12 at offset 0x180000 Writing data to block 13 at offset 0x1a0000 Writing data to block 14 at offset 0x1c0000 Writing data to block 15 at offset 0x1e0000 Writing data to block 16 at offset 0x200000 Writing data to block 17 at offset 0x220000 Writing data to block 18 at offset 0x240000 Writing data to block 19 at offset 0x260000 Writing data to block 20 at offset 0x280000 Writing data to block 21 at offset 0x2a0000 Writing data to block 22 at offset 0x2c0000 Writing data to block 23 at offset 0x2e0000 Writing data to block 24 at offset 0x300000 Writing data to block 25 at offset 0x320000 Writing data to block 26 at offset 0x340000 Writing data to block 27 at offset 0x360000 root at debug:~# CM-A510>> nboot 200000 nand0 0 no partition number specified Loading from nand0, offset 0x0 Bad block table found at page 262080, version 0x01 Bad block table found at page 262016, version 0x01 Image Name: Linux kernel Created: 2015-03-30 6:41:19 UTC Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 3637235 Bytes = 3.5 MB Load Address: 00008000 Entry Point: 00008000 CM-A510>> bootm ## Booting kernel from Legacy Image at 00200000 ... Image Name: Linux kernel Created: 2015-03-30 6:41:19 UTC Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 3637235 Bytes = 3.5 MB Load Address: 00008000 Entry Point: 00008000 Verifying Checksum ... OK Loading Kernel Image ... OK OK Starting kernel ... Booting Linux on physical CPU 0x0 ... > On 30/03/15 01:34, Ezequiel Garcia wrote: >> Maybe a silly question, but does your bootloader initializes the >> controller? Are you able to read/write/erase using it? >> >> The current pxa3xx-nand driver relies on that for Armada370/XP, as >> timing setup is not properly handled. Ezequiel, Yes, it initializes the controller. Gabriel Dobato ^ permalink raw reply [flat|nested] 6+ messages in thread
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2015-03-29 10:20 ` Fwd: Ask for help: ARM: mvebu: add NAND support for dove Sebastian Hesselbarth
2015-03-29 10:20 ` Sebastian Hesselbarth
2015-03-29 23:34 ` Ezequiel Garcia
2015-03-29 23:34 ` Ezequiel Garcia
2015-03-30 7:01 ` Gabriel Dobato
2015-03-30 7:01 ` Gabriel Dobato
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