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From: leizhen <thunder.leizhen@huawei.com>
To: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <marc.zyngier@arm.com>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	Zefan Li <lizefan@huawei.com>, Xinwei Hu <huxinwei@huawei.com>,
	Tianhong Ding <dingtianhong@huawei.com>,
	Kefeng Wang <wangkefeng.wang@huawei.com>,
	Yun Wu <wuyun.wu@huawei.com>
Subject: Re: [PATCH 1/1] irqchip/gicv3-its: remove GITS_BASER_TYPE_CPU base on latest specification
Date: Tue, 7 Apr 2015 10:05:45 +0800	[thread overview]
Message-ID: <55233B79.1050706@huawei.com> (raw)
In-Reply-To: <20150403144624.GM24598@io.lakedaemon.net>

On 2015/4/3 22:46, Jason Cooper wrote:
> Zhen Lei,
> 
> On Fri, Apr 03, 2015 at 11:33:52AM +0800, Zhen Lei wrote:
>> Acutally, "Interrupt Collections" and "Physical Processors" is the
>> same thing.
> 
> I'm sorry, but this isn't clear.
> 
>> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
>> ---
>>  drivers/irqchip/irq-gic-v3-its.c   | 2 +-
>>  include/linux/irqchip/arm-gic-v3.h | 2 +-
>>  2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
>> index 9687f8a..a795aae 100644
>> --- a/drivers/irqchip/irq-gic-v3-its.c
>> +++ b/drivers/irqchip/irq-gic-v3-its.c
>> @@ -777,7 +777,7 @@ static int __init its_alloc_lpi_tables(void)
>>  static const char *its_base_type_string[] = {
>>  	[GITS_BASER_TYPE_DEVICE]	= "Devices",
>>  	[GITS_BASER_TYPE_VCPU]		= "Virtual CPUs",
>> -	[GITS_BASER_TYPE_CPU]		= "Physical CPUs",
>> +	[GITS_BASER_TYPE_RESERVED3]	= "Reserved (3)",
> 
> Are you fixing a bug?  Was the old information wrong?  Did the spec get
> revised?

In spec version 19.0, clause 5.12.13 GITS_BASERn. The "Type" field define value=0x3 means:
0x3. Physical Processors. This register corresponds to a table that scales according to the number of physical processors in the system and requires (Entry-size * number-of-processors) bytes of memory.

In spec version 24.0, clause 5.12.13 GITS_BASERn. The "Type" field define value=0x3 as reserved:
0x3. Reserved.

> 
> Please redo your commit message to explain why this change is necessary and
> what it's doing.

OK, thank  you for your advise.

> 
>>  	[GITS_BASER_TYPE_COLLECTION]	= "Interrupt Collections",
>>  	[GITS_BASER_TYPE_RESERVED5] 	= "Reserved (5)",
>>  	[GITS_BASER_TYPE_RESERVED6] 	= "Reserved (6)",
>> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
>> index ffbc034..67f5779 100644
>> --- a/include/linux/irqchip/arm-gic-v3.h
>> +++ b/include/linux/irqchip/arm-gic-v3.h
>> @@ -233,7 +233,7 @@
>>  #define GITS_BASER_TYPE_NONE		0
>>  #define GITS_BASER_TYPE_DEVICE		1
>>  #define GITS_BASER_TYPE_VCPU		2
>> -#define GITS_BASER_TYPE_CPU		3
>> +#define GITS_BASER_TYPE_RESERVED3	3
>>  #define GITS_BASER_TYPE_COLLECTION	4
>>  #define GITS_BASER_TYPE_RESERVED5	5
>>  #define GITS_BASER_TYPE_RESERVED6	6
>> --
>> 1.8.0
> 
> thx,
> 
> Jason.
> 
> .
> 



      reply	other threads:[~2015-04-07  2:06 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-03  3:33 [PATCH 1/1] irqchip/gicv3-its: remove GITS_BASER_TYPE_CPU base on latest specification Zhen Lei
2015-04-03 14:46 ` Jason Cooper
2015-04-07  2:05   ` leizhen [this message]

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