From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lori Hikichi Subject: Re: [PATCH 2/2] ASoC: add core audio driver for Broadcom Cygnus SOC. Date: Thu, 9 Apr 2015 19:06:22 -0700 Message-ID: <5527301E.6070906@broadcom.com> References: <1427771784-29950-1-git-send-email-sbranden@broadcom.com> <1427771784-29950-3-git-send-email-sbranden@broadcom.com> <20150331064209.GD2869@sirena.org.uk> <551D8EB6.1050004@broadcom.com> <20150406161939.GJ6023@sirena.org.uk> <552492E1.3050207@broadcom.com> <20150408192309.GI6023@sirena.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <20150408192309.GI6023-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Mark Brown Cc: Scott Branden , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w@public.gmane.org, Dmitry Torokhov , Anatol Pomazao , abrestic-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org, bryeung-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org, olofj-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org, pwestin-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org List-Id: alsa-devel@alsa-project.org On 15-04-08 12:23 PM, Mark Brown wrote: > On Tue, Apr 07, 2015 at 07:30:57PM -0700, Lori Hikichi wrote: >> On 15-04-06 09:19 AM, Mark Brown wrote: >=20 >>> OK, so that seems fragile - what happens if we're slightly late >>> processing an interrupt or miss one entirely? Most hardware has so= me >>> way to read back the current position which tends to be more reliab= le, >>> is that not an option here? >=20 >> The hardware updates a read pointer (rdaddr) which we feed to ALSA v= ia the >> ".pointer" hook. So yes, the hardware does have a register that tell= s us its >> progress. This routine (ringbuf_inc) actually updates a write point= er >> (wraddr) which is a misnomer. The write pointer doesn=E2=80=99t act= ually tell us >> where we are writing to =E2=80=93 ALSA keeps track of that. The wrad= dr only prevents >> the hardware from reading past it. We just use it, along with a low= water >> mark configuration register, to keep the periodic interrupts firing.= The >> hardware is tracking the distance between rdaddr and wraddr and comp= aring >> that to the low water mark. >=20 > The code has handling for both read and write so it's not just updati= ng > a write pointer. Is there no flexibility in the hardware regarding > interrupt generation? >=20 >> Being late processing the interrupt is okay since there are more sam= ples to >> read. That is, it was only a low water mark interrupt and we have o= ne >> period of valid data still (we configure low water to be one period)= =2E >> Missing an interrupt is okay since the hardware will just stop readi= ng from >> buffer when rdaddr has hit wraddr. >=20 > Stopping if we miss an interrupt is precisely the sort of situation w= e > want to avoid if we can - if the application is sufficiently far ahea= d > of the hardware everything should continue to work fine. The minimal > period size appears to be very small so this is a potential issue, if= an > application tries to use many very small periods it's both more > vulnerable to some other interrupt taking longer than might be desira= ble > and likely that things would be fine as the application is hopefully > more than one period ahead of where the hardware is at. >=20 > If the hardware is always going to halt at the end of the period ther= e's > not a huge amount we can do about this except possibly raise the mini= mum > period if systems are running into trouble but if there's a way to av= oid > doing that then that would be even better. >=20 Makes sense, thanks for clarifying the desired behaviour, I will make t= he=20 necessary adjustments to keep the hardware supplied with valid data eve= n if=20 interrupts are held off past a whole period. -- To unsubscribe from this list: send the line "unsubscribe devicetree" i= n the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: lhikichi@broadcom.com (Lori Hikichi) Date: Thu, 9 Apr 2015 19:06:22 -0700 Subject: [PATCH 2/2] ASoC: add core audio driver for Broadcom Cygnus SOC. In-Reply-To: <20150408192309.GI6023@sirena.org.uk> References: <1427771784-29950-1-git-send-email-sbranden@broadcom.com> <1427771784-29950-3-git-send-email-sbranden@broadcom.com> <20150331064209.GD2869@sirena.org.uk> <551D8EB6.1050004@broadcom.com> <20150406161939.GJ6023@sirena.org.uk> <552492E1.3050207@broadcom.com> <20150408192309.GI6023@sirena.org.uk> Message-ID: <5527301E.6070906@broadcom.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 15-04-08 12:23 PM, Mark Brown wrote: > On Tue, Apr 07, 2015 at 07:30:57PM -0700, Lori Hikichi wrote: >> On 15-04-06 09:19 AM, Mark Brown wrote: > >>> OK, so that seems fragile - what happens if we're slightly late >>> processing an interrupt or miss one entirely? Most hardware has some >>> way to read back the current position which tends to be more reliable, >>> is that not an option here? > >> The hardware updates a read pointer (rdaddr) which we feed to ALSA via the >> ".pointer" hook. So yes, the hardware does have a register that tells us its >> progress. This routine (ringbuf_inc) actually updates a write pointer >> (wraddr) which is a misnomer. The write pointer doesn?t actually tell us >> where we are writing to ? ALSA keeps track of that. The wraddr only prevents >> the hardware from reading past it. We just use it, along with a low water >> mark configuration register, to keep the periodic interrupts firing. The >> hardware is tracking the distance between rdaddr and wraddr and comparing >> that to the low water mark. > > The code has handling for both read and write so it's not just updating > a write pointer. Is there no flexibility in the hardware regarding > interrupt generation? > >> Being late processing the interrupt is okay since there are more samples to >> read. That is, it was only a low water mark interrupt and we have one >> period of valid data still (we configure low water to be one period). >> Missing an interrupt is okay since the hardware will just stop reading from >> buffer when rdaddr has hit wraddr. > > Stopping if we miss an interrupt is precisely the sort of situation we > want to avoid if we can - if the application is sufficiently far ahead > of the hardware everything should continue to work fine. The minimal > period size appears to be very small so this is a potential issue, if an > application tries to use many very small periods it's both more > vulnerable to some other interrupt taking longer than might be desirable > and likely that things would be fine as the application is hopefully > more than one period ahead of where the hardware is at. > > If the hardware is always going to halt at the end of the period there's > not a huge amount we can do about this except possibly raise the minimum > period if systems are running into trouble but if there's a way to avoid > doing that then that would be even better. > Makes sense, thanks for clarifying the desired behaviour, I will make the necessary adjustments to keep the hardware supplied with valid data even if interrupts are held off past a whole period. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753653AbbDJCGa (ORCPT ); Thu, 9 Apr 2015 22:06:30 -0400 Received: from mail-gw2-out.broadcom.com ([216.31.210.63]:10031 "EHLO mail-gw2-out.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751938AbbDJCGZ (ORCPT ); Thu, 9 Apr 2015 22:06:25 -0400 X-IronPort-AV: E=Sophos;i="5.11,554,1422950400"; d="scan'208";a="61719733" Message-ID: <5527301E.6070906@broadcom.com> Date: Thu, 9 Apr 2015 19:06:22 -0700 From: Lori Hikichi User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.0 MIME-Version: 1.0 To: Mark Brown CC: Scott Branden , Rob Herring , Pawel Moll , Mark Rutland , "Ian Campbell" , Kumar Gala , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , , , , , , Dmitry Torokhov , Anatol Pomazao , , , , Subject: Re: [PATCH 2/2] ASoC: add core audio driver for Broadcom Cygnus SOC. References: <1427771784-29950-1-git-send-email-sbranden@broadcom.com> <1427771784-29950-3-git-send-email-sbranden@broadcom.com> <20150331064209.GD2869@sirena.org.uk> <551D8EB6.1050004@broadcom.com> <20150406161939.GJ6023@sirena.org.uk> <552492E1.3050207@broadcom.com> <20150408192309.GI6023@sirena.org.uk> In-Reply-To: <20150408192309.GI6023@sirena.org.uk> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 15-04-08 12:23 PM, Mark Brown wrote: > On Tue, Apr 07, 2015 at 07:30:57PM -0700, Lori Hikichi wrote: >> On 15-04-06 09:19 AM, Mark Brown wrote: > >>> OK, so that seems fragile - what happens if we're slightly late >>> processing an interrupt or miss one entirely? Most hardware has some >>> way to read back the current position which tends to be more reliable, >>> is that not an option here? > >> The hardware updates a read pointer (rdaddr) which we feed to ALSA via the >> ".pointer" hook. So yes, the hardware does have a register that tells us its >> progress. This routine (ringbuf_inc) actually updates a write pointer >> (wraddr) which is a misnomer. The write pointer doesn’t actually tell us >> where we are writing to – ALSA keeps track of that. The wraddr only prevents >> the hardware from reading past it. We just use it, along with a low water >> mark configuration register, to keep the periodic interrupts firing. The >> hardware is tracking the distance between rdaddr and wraddr and comparing >> that to the low water mark. > > The code has handling for both read and write so it's not just updating > a write pointer. Is there no flexibility in the hardware regarding > interrupt generation? > >> Being late processing the interrupt is okay since there are more samples to >> read. That is, it was only a low water mark interrupt and we have one >> period of valid data still (we configure low water to be one period). >> Missing an interrupt is okay since the hardware will just stop reading from >> buffer when rdaddr has hit wraddr. > > Stopping if we miss an interrupt is precisely the sort of situation we > want to avoid if we can - if the application is sufficiently far ahead > of the hardware everything should continue to work fine. The minimal > period size appears to be very small so this is a potential issue, if an > application tries to use many very small periods it's both more > vulnerable to some other interrupt taking longer than might be desirable > and likely that things would be fine as the application is hopefully > more than one period ahead of where the hardware is at. > > If the hardware is always going to halt at the end of the period there's > not a huge amount we can do about this except possibly raise the minimum > period if systems are running into trouble but if there's a way to avoid > doing that then that would be even better. > Makes sense, thanks for clarifying the desired behaviour, I will make the necessary adjustments to keep the hardware supplied with valid data even if interrupts are held off past a whole period.