From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH v1 0/1] xen/arm: GICv2 GICH_MISR Read-Only Date: Fri, 10 Apr 2015 11:51:45 +0100 Message-ID: <5527AB41.8000908@citrix.com> References: <1428646870-22093-1-git-send-email-edgar.iglesias@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1428646870-22093-1-git-send-email-edgar.iglesias@gmail.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: "Edgar E. Iglesias" , xen-devel@lists.xen.org Cc: stefano.stabellini@citrix.com, julien.grall@linaro.org, tim@xen.org, ian.campbell@citrix.com, Zoltan Kiss List-Id: xen-devel@lists.xenproject.org On 10/04/15 07:21, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Hi, Hi Edgar, > Does any one know why we are writing to GICH_MISR? It is a Read-Only > register in GICv2. This showed up as illegal accesses in my QEMU logs. I think this is a misunderstanding of the spec at the time the GIC driver has been written. On real hardware the write access is ignored. AFAICT, we don't even care to get a maintenance interrupt when one LR is asserting an EOI (assuming we think this bit was enabling the assertion). > I suspect gic-hip04 needs a similar patch. Are there any specs for > that GIC somewhere? This hardware is very similar to the GIC. A chinese spec has been sent on the ML a couple of months ago [1]. Although, the HIP 04 driver is not functional anymore as the maintainers of this driver (from Huawei and in CC) didn't answer to previous change to the common GIC code [2]. Regards, [1] https://github.com/hisilicon/boards/tree/master/D01/docs [2] http://lists.xenproject.org/archives/html/xen-devel/2015-03/msg03835.html -- Julien Grall