[PATCH v1 0/1] xen/arm: GICv2 GICH_MISR Read-Only

[PATCH v1 0/1] xen/arm: GICv2 GICH_MISR Read-Only

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Hi,

Does any one know why we are writing to GICH_MISR? It is a Read-Only
register in GICv2. This showed up as illegal accesses in my QEMU logs.

I suspect gic-hip04 needs a similar patch. Are there any specs for
that GIC somewhere?

Cheers,
Edgar

Edgar E. Iglesias (1):
  xen/arm: Don't write to GICH_MISR

 xen/arch/arm/gic-v2.c | 2 --
 1 file changed, 2 deletions(-)

-- 
1.9.1

[PATCH v1 1/1] xen/arm: Don't write to GICH_MISR

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

GICH_MISR is read-only in GICv2.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 xen/arch/arm/gic-v2.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index cfefb39..1a639e0 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -345,8 +345,6 @@ static void __cpuinit gicv2_hyp_init(void)
     vtr = readl_gich(GICH_VTR);
     nr_lrs  = (vtr & GICH_V2_VTR_NRLRGS) + 1;
     gicv2_info.nr_lrs = nr_lrs;
-
-    writel_gich(GICH_MISR_EOI, GICH_MISR);
 }
 
 static void __cpuinit gicv2_hyp_disable(void)
-- 
1.9.1

Re: [PATCH v1 1/1] xen/arm: Don't write to GICH_MISR

[Julien Grall]

On 10/04/15 07:21, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> 
> GICH_MISR is read-only in GICv2.
> 
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Julien Grall <julien.grall@citrix.com>

Regards,

-- 
Julien Grall

Re: [PATCH v1 1/1] xen/arm: Don't write to GICH_MISR

[Ian Campbell]

On Fri, 2015-04-10 at 11:52 +0100, Julien Grall wrote:
> On 10/04/15 07:21, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> > 
> > GICH_MISR is read-only in GICv2.
> > 
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> 
> Reviewed-by: Julien Grall <julien.grall@citrix.com>

acked + applied, thanks.

Re: [PATCH v1 0/1] xen/arm: GICv2 GICH_MISR Read-Only

[Julien Grall]

On 10/04/15 07:21, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> 
> Hi,

Hi Edgar,

> Does any one know why we are writing to GICH_MISR? It is a Read-Only
> register in GICv2. This showed up as illegal accesses in my QEMU logs.

I think this is a misunderstanding of the spec at the time the GIC
driver has been written. On real hardware the write access is ignored.

AFAICT, we don't even care to get a maintenance interrupt when one LR is
asserting an EOI (assuming we think this bit was enabling the assertion).

> I suspect gic-hip04 needs a similar patch. Are there any specs for
> that GIC somewhere?

This hardware is very similar to the GIC. A chinese spec has been sent
on the ML a couple of months ago [1].

Although, the HIP 04 driver is not functional anymore as the maintainers
 of this driver (from Huawei and in CC) didn't answer to previous change
to the common GIC code [2].

Regards,

[1] https://github.com/hisilicon/boards/tree/master/D01/docs

[2]
http://lists.xenproject.org/archives/html/xen-devel/2015-03/msg03835.html

-- 
Julien Grall