[Query] PORT_LOGIC_SPEED_CHANGE set in PCIe designware driver

[Zhou Wang <wangzhou1@hisilicon.com>]

Hi All,

In pcie-designware.c, it sets the PORT_LOGIC_SPEED_CHANGE bit after linkup
finished:

dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
val |= PORT_LOGIC_SPEED_CHANGE;
dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);

As far as I know, it will try to use 5G/8G to communicate after setting this
bit. When I used LSI SAS2208 PCIe-RAID card to test PCIe host driver, PCIe3.0
link was unstable and can not read/write PCIe-RAID BAR. When I moved above
code before linkup, the process of enumeration was successful.

I wonder if anyone who also use the pcie-designware had met the same problem.
Could we move the PORT_LOGIC_SPEED_CHANGE before linkup?

It will be very appreciate if anyone can offer some information.

Thanks,
Zhou