From mboxrd@z Thu Jan  1 00:00:00 1970
From: Julien Grall <julien.grall@citrix.com>
Subject: Re: [PATCH 11/19] xen: arm: Annotate handlers for
	PCTR_EL2.Tx
Date: Fri, 17 Apr 2015 07:31:28 +0100
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To: Ian Campbell <ian.campbell@citrix.com>, Julien Grall <julien.grall@citrix.com>
Cc: xen-devel@lists.xen.org, julien.grall@linaro.org, tim@xen.org, stefano.stabellini@eu.citrix.com
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Hi Ian,

On 16/04/2015 17:53, Ian Campbell wrote:
> On Mon, 2015-04-06 at 13:18 +0200, Julien Grall wrote:
>> Hi Ian,
>>
>> Subject: s/PCTR/CPTR/
>>
>> On 31/03/2015 12:07, Ian Campbell wrote:
>>> Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
>>> ---
>>>    xen/arch/arm/traps.c |   14 ++++++++++++++
>>>    1 file changed, 14 insertions(+)
>>>
>>> diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
>>> index 9cdbda8..ba120e5 100644
>>> --- a/xen/arch/arm/traps.c
>>> +++ b/xen/arch/arm/traps.c
>>> @@ -1704,6 +1704,11 @@ static void do_cp15_32(struct cpu_user_regs *regs,
>>>         * ARMv7 (DDI 0406C.b): B1.14.3
>>>         * ARMv8 (DDI 0487A.d): D1-1501 Table D1-43
>>>         *
>>> +     * CPTR_EL2.T{0..9,12..13}
>>> +     *
>>> +     * ARMv7 (DDI 0406C.b): B1.14.12
>>> +     * ARMv8 (DDI 0487A.d): N/A
>>
>> I would also update the comment on top of WRITE_SYSREG(..., CPTR_EL2) to
>> make clear that CP0..CP9 & CP12..CP13 are only traps for ARMv7.
>
> On v8 the corresponding bits are RES1, i.e. they always trap. I wrote:

Somehow I read RES0 in the spec.

>
>      /* Trap all coprocessor registers (0-13) except cp10 and
>       * cp11 for VFP.
>       *
>       * /!\ All coprocessors except cp10 and cp11 cannot be used in Xen.
>       *
>       * On ARM64 the TCPx bits which we set here (0..9,12,13) are all
>       * RES1, i.e. they would trap whether we did this write or not.
>       */

I'm fine with this change.

Regards,

-- 
Julien Grall