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[85.141.198.209]) by mx.google.com with ESMTPSA id zf3sm2504905lbb.2.2015.04.17.09.17.28 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Apr 2015 09:17:30 -0700 (PDT) Message-ID: <55313217.1020604@cogentembedded.com> Date: Fri, 17 Apr 2015 19:17:27 +0300 From: Sergei Shtylyov Organization: Cogent Embedded User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 To: Alban Bedel , linux-mips@linux-mips.org CC: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Thomas Gleixner , Jason Cooper , Ralf Baechle , Andrew Bresticker , Qais Yousef , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 04/14] devicetree: Add bindings for the ATH79 interrupt controllers References: <1429280669-2986-1-git-send-email-albeu@free.fr> <1429280669-2986-5-git-send-email-albeu@free.fr> In-Reply-To: <1429280669-2986-5-git-send-email-albeu@free.fr> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 46898 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sergei.shtylyov@cogentembedded.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Hello. On 04/17/2015 05:24 PM, Alban Bedel wrote: > Signed-off-by: Alban Bedel > --- > .../interrupt-controller/qca,ath79-cpu-intc.txt | 45 ++++++++++++++++++++++ > 1 file changed, 45 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt > diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt > new file mode 100644 > index 0000000..1548512 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt > @@ -0,0 +1,45 @@ > +Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller > + > +On most SoC the IRQ controller need to flush the DDR FIFO before running > +the interrupt handler of some devices. This is configured using the > +qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties. > + > +Required Properties: > + > +- compatible: has to be "qca,-cpu-intc", "qca,ar7100-cpu-intc" > + as fallback > +- interrupt-controller : Identifies the node as an interrupt controller > +- #interrupt-cells : Specifies the number of cells needed to encode interrupt > + source, should be 1 for intc > + > +Please refer to interrupts.txt in this directory for details of the common > +Interrupt Controllers bindings used by client devices. > + > +Optional Properties: > + > +- qca,ddr-wb-channel-interrupts: List of the interrupts needing a write > + buffer flush > +- qca,ddr-wb-channels: List of phandles to the write buffer channels for > + each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt > + default to the entry's index. > + > +Example: > + > + cpuintc@0 { @0 without the "reg" property? And if this is an interrupt controller, the name should be "interrupt-controller", not "cpuintc", according to the ePAPR standard. > + compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; > + > + interrupt-controller; > + #interrupt-cells = <1>; > + > + qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; > + qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, > + <&ddr_ctrl 0>, <&ddr_ctrl 1>; > + }; > + > + ... > + > + ddr_ctrl: ddr-controller@18000000 { ePAPR standardized "memory-controller" node name in this case. WBR, Sergei