From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by yocto-www.yoctoproject.org (Postfix, from userid 118) id 6FA9DE008DC; Fri, 17 Apr 2015 13:20:22 -0700 (PDT) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on yocto-www.yoctoproject.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00 autolearn=ham version=3.3.1 X-Spam-HAM-Report: * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] X-Greylist: delayed 358 seconds by postgrey-1.32 at yocto-www; Fri, 17 Apr 2015 13:20:19 PDT Received: from mx.dave-tech.it (mx.dave-tech.it [2.229.21.40]) by yocto-www.yoctoproject.org (Postfix) with ESMTP id 02DBFE007A0 for ; Fri, 17 Apr 2015 13:20:19 -0700 (PDT) Received: from [127.0.0.1] (unknown [192.168.0.126]) by mx.dave-tech.it (Postfix) with ESMTPS id 7D64913; Fri, 17 Apr 2015 22:14:19 +0200 (CEST) Message-ID: <5531699B.5030204@dave-tech.it> Date: Fri, 17 Apr 2015 22:14:19 +0200 From: Andrea Scian User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: ansaris@iwavesystems.com References: <55310495.1050005@iwavesystems.com> In-Reply-To: <55310495.1050005@iwavesystems.com> X-Antivirus: avast! (VPS 150417-1, 17/04/2015), Outbound message X-Antivirus-Status: Clean Cc: meta-freescale@yoctoproject.org Subject: Re: iMX6 - CPU frequency lowered during LDO bypass setting X-BeenThere: meta-freescale@yoctoproject.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Usage and development list for the meta-fsl-* layers List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 17 Apr 2015 20:20:22 -0000 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Il 17/04/2015 15:03, ansaris ha scritto: > We would like to know, during the LDO bypass settings why the CPU > frequency is lowered in File-1(Linux 3.14.28_1.0.0-GA)? Is it > recommended to do the same.? I think that the answer is here: http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/?id=404fd02e96d33840f58f83f88815e2a259cdc532 During bypass procedure you violate datasheet power constraint if running at 800MHz: in LDO mode VDD_ARM must be 125mV higher that the LDO output voltage, while you need to lower VDD_ARM (on PMIC) before switching to bypass mode. To fill the 125mV gap you need to: - switch to 400MHz - lower PMIC voltages - switch to bypass mode (which remove the 125mV gap) - switch back to 800MHz If you skip the first step you may have 1.175-0.125 = 1.050V which is below the required power supply for VDD_ARM I think this is the meaning of the commit, please correct me if I'm wrong, of course. Kind Regards, -- Andrea SCIAN DAVE Embedded Systems