Re: [PATCH] ALSA: hda - add AZX_DCAPS_I915_POWERWELL to Baytrail

[David Henningsson <david.henningsson@canonical.com>]

Hi,

Baytrail is very much released and out there already - should this patch 
also go to stable?

Are there current problems (like HDMI codec not being detected) that are 
fixed by this patch?

// David

On 2015-04-21 07:12, mengdong.lin@intel.com wrote:
> From: Mengdong Lin <mengdong.lin@intel.com>
>
> This patch addes AZX_DCAPS_I915_POWERWELL to BYT (Baytrail).
>
> Like Braswell and Skylake, the HDMI codec on Bytrail is also in the shared
> power well with GPU. This power well must be turned on before we reset link
> to probe the codec, to avoid communication failure with the codec.
>
> The side effect is that this power is always ON in S0 because the BYT HDMI
> codec does not support EPSS or D3ClkStop and so the controller doesn't enter
> D3 at runtime, and the HDMI codec and analog codec share a single physical
> HD-A link and so we cannot reset the HD-A link freely when we re-enable the
> power to use the HDMI codec.
>
> Next step is to test if an AGP reset or double AGP reset on BYT HDMI codec is
> okay to bring the HDMI codec back to a functional state after restoring the
> power. If okay, we can bind the power on/off with the HDMI codec PM without
> interrupting the analog audio.
>
> Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
>
> diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
> index e1c2105..34040d2 100644
> --- a/sound/pci/hda/hda_intel.c
> +++ b/sound/pci/hda/hda_intel.c
> @@ -297,6 +297,9 @@ enum {
>   	 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
>   	 AZX_DCAPS_SNOOP_TYPE(SCH))
>
> +#define AZX_DCAPS_INTEL_BAYTRAIL \
> +	(AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
> +
>   #define AZX_DCAPS_INTEL_BRASWELL \
>   	(AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
>
> @@ -1992,7 +1995,7 @@ static const struct pci_device_id azx_ids[] = {
>   	  .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
>   	/* BayTrail */
>   	{ PCI_DEVICE(0x8086, 0x0f04),
> -	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
> +	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
>   	/* Braswell */
>   	{ PCI_DEVICE(0x8086, 0x2284),
>   	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
>

-- 
David Henningsson, Canonical Ltd.
https://launchpad.net/~diwic