From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Cooper Subject: Re: [PATCHv3 3/4] xen: use ticket locks for spin locks Date: Thu, 23 Apr 2015 14:45:38 +0100 Message-ID: <5538F782.7070405@citrix.com> References: <1429611088-23950-1-git-send-email-david.vrabel@citrix.com> <1429611088-23950-4-git-send-email-david.vrabel@citrix.com> <20150423120302.GG10810@deinos.phlegethon.org> <5538F715.3030408@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YlHeR-0007ob-Ih for xen-devel@lists.xenproject.org; Thu, 23 Apr 2015 13:58:47 +0000 In-Reply-To: <5538F715.3030408@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: David Vrabel , Tim Deegan Cc: Keir Fraser , Ian Campbell , Stefano Stabellini , Jennifer Herbert , Jan Beulich , xen-devel@lists.xenproject.org List-Id: xen-devel@lists.xenproject.org On 23/04/15 14:43, David Vrabel wrote: > On 23/04/15 13:03, Tim Deegan wrote: >> Hi, >> >> At 11:11 +0100 on 21 Apr (1429614687), David Vrabel wrote: >>> void _spin_lock(spinlock_t *lock) >>> { >>> + spinlock_tickets_t tickets = { .tail = 1, }; >>> LOCK_PROFILE_VAR; >>> >>> check_lock(&lock->debug); >>> - while ( unlikely(!_raw_spin_trylock(&lock->raw)) ) >>> + tickets.head_tail = xadd(&lock->tickets.head_tail, tickets.head_tail); >>> + while ( tickets.tail != observe_head(&lock->tickets) ) >>> { >>> LOCK_PROFILE_BLOCK; >>> - while ( likely(_raw_spin_is_locked(&lock->raw)) ) >>> - cpu_relax(); >>> + cpu_relax(); >>> } >>> LOCK_PROFILE_GOT; >>> preempt_disable(); >> I think you need an smp_mb() here to make sure that locked accesses >> don't get hoisted past the wait-for-my-ticket loop by an out-of-order >> (ARM) cpu. > Ok, but smp_mb() turns into an mfence on x86. Is this a > problem/sub-optimal? That can probably change back to a plain compiler barrier as Xen only supports 64bit and doesn't need PPRO ordering errata workarounds. ~Andrew