From: York Sun <yorksun@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/2][v2] pci/layerscape: fix link and class issues to support ls2085a
Date: Thu, 23 Apr 2015 16:30:52 -0700 [thread overview]
Message-ID: <553980AC.7020607@freescale.com> (raw)
In-Reply-To: <1426129129-10149-2-git-send-email-Minghuan.Lian@freescale.com>
On 03/11/2015 07:58 PM, Minghuan Lian wrote:
> 1. LS2085a provides PCIE_LUT_DBG register rather than PCIE_LDBG
> to show the link status, so the patch fixes it.
> 2. Increase the delay time to make sure that link training
> has finished.
> 3. Return invalid value when accessing multi-function device
> 4. For LS2085a DBI_RO_WR_EN bit is cleared as default, so we
> must set this bit before change DBI register value.
>
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> ---
> change log:
> v1-v2: no change
>
Applied to fsl-qoriq master, awaiting upstream.
York
next prev parent reply other threads:[~2015-04-23 23:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-12 2:58 [U-Boot] [PATCH 1/2][v2] pci/layerscape: remove unnecessary pcie_layerscape.h Minghuan Lian
2015-03-12 2:58 ` [U-Boot] [PATCH 2/2][v2] pci/layerscape: fix link and class issues to support ls2085a Minghuan Lian
2015-04-23 23:30 ` York Sun [this message]
2015-03-12 12:25 ` [U-Boot] [PATCH 1/2][v2] pci/layerscape: remove unnecessary pcie_layerscape.h Tom Rini
2015-04-23 23:30 ` York Sun
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