From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33934) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yn5fZ-00032N-Ns for qemu-devel@nongnu.org; Tue, 28 Apr 2015 09:35:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yn5fV-00014E-CY for qemu-devel@nongnu.org; Tue, 28 Apr 2015 09:35:25 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:12886 helo=imgpgp01.kl.imgtec.org) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yn5fV-000126-3c for qemu-devel@nongnu.org; Tue, 28 Apr 2015 09:35:21 -0400 Message-ID: <553F8C8E.2030706@imgtec.com> Date: Tue, 28 Apr 2015 14:35:10 +0100 From: James Hogan MIME-Version: 1.0 References: <1430224874-18513-1-git-send-email-leon.alrae@imgtec.com> <1430224874-18513-3-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1430224874-18513-3-git-send-email-leon.alrae@imgtec.com> Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="nLkN8UIJqRupMJFfrJOrroiVNW8CRLbMe" Subject: Re: [Qemu-devel] [PATCH 2/7] target-mips: support Page Frame Number Extension field List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Leon Alrae , qemu-devel@nongnu.org Cc: aurelien@aurel32.net --nLkN8UIJqRupMJFfrJOrroiVNW8CRLbMe Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable On 28/04/15 13:41, Leon Alrae wrote: > Update tlb->PFN to contain PFN concatenated with PFNX. PFNX is 0 if lar= ge > physical address is not supported. >=20 > Signed-off-by: Leon Alrae > --- > target-mips/op_helper.c | 32 ++++++++++++++++++++++++++------ > 1 file changed, 26 insertions(+), 6 deletions(-) >=20 > diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c > index c9a60bd..6bff927 100644 > --- a/target-mips/op_helper.c > +++ b/target-mips/op_helper.c > @@ -1825,6 +1825,16 @@ static void r4k_mips_tlb_flush_extra (CPUMIPSSta= te *env, int first) > } > } > =20 > +static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo) > +{ > +#if defined(TARGET_MIPS64) > + return extract64(entrylo, 6, 54); > +#else > + return extract64(entrylo, 6, 24) | /* PFN */ > + (extract64(entrylo, 32, 32) << 24); /* PFNX */ Where does the 32,32 come from? The PRA I have seems to imply that PFNX starts at bit 30 and goes up to bit 54. That would of course also mean that the code for mfc0 EntryLo* needs tweaking so that PFNX doesn't cause XI/RI bits to be set at bits 30,31 (haven't looked at other patches yet). > +#endif > +} > + > static void r4k_fill_tlb(CPUMIPSState *env, int idx) > { > r4k_tlb_t *tlb; > @@ -1848,13 +1858,13 @@ static void r4k_fill_tlb(CPUMIPSState *env, int= idx) > tlb->C0 =3D (env->CP0_EntryLo0 >> 3) & 0x7; > tlb->XI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1; > tlb->RI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1; > - tlb->PFN[0] =3D (env->CP0_EntryLo0 >> 6) << 12; > + tlb->PFN[0] =3D get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;= > tlb->V1 =3D (env->CP0_EntryLo1 & 2) !=3D 0; > tlb->D1 =3D (env->CP0_EntryLo1 & 4) !=3D 0; > tlb->C1 =3D (env->CP0_EntryLo1 >> 3) & 0x7; > tlb->XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1; > tlb->RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1; > - tlb->PFN[1] =3D (env->CP0_EntryLo1 >> 6) << 12; > + tlb->PFN[1] =3D get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;= > } > =20 > void r4k_helper_tlbinv(CPUMIPSState *env) > @@ -1971,6 +1981,16 @@ void r4k_helper_tlbp(CPUMIPSState *env) > } > } > =20 > +static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn) > +{ > +#if defined(TARGET_MIPS64) > + return tlb_pfn << 6; > +#else > + return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */ > + (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */ same again. shouldn't it be 25 bits starting at bit 24, shifted to start at bit 30? Cheers James > +#endif > +} > + > void r4k_helper_tlbr(CPUMIPSState *env) > { > r4k_tlb_t *tlb; > @@ -1997,12 +2017,12 @@ void r4k_helper_tlbr(CPUMIPSState *env) > env->CP0_PageMask =3D tlb->PageMask; > env->CP0_EntryLo0 =3D tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2)= | > ((uint64_t)tlb->RI0 << CP0EnLo_RI) | > - ((uint64_t)tlb->XI0 << CP0EnLo_XI) | > - (tlb->C0 << 3) | (tlb->PFN[0] >> 6); > + ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 = << 3) | > + get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12); > env->CP0_EntryLo1 =3D tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2)= | > ((uint64_t)tlb->RI1 << CP0EnLo_RI) | > - ((uint64_t)tlb->XI1 << CP0EnLo_XI) | > - (tlb->C1 << 3) | (tlb->PFN[1] >> 6); > + ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 = << 3) | > + get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12); > } > } > =20 >=20 --nLkN8UIJqRupMJFfrJOrroiVNW8CRLbMe Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBAgAGBQJVP4yVAAoJEGwLaZPeOHZ6vQkQAJZcQbvEtSqbr0v04xqWVEYm bCtsqM8Aned59MgfZ+TzPWx7Kv3RkB7mI4yZ+0c1zRmn8qrtVLIqkKXDN4oV21Yq 8/a7tHO9oGxTk++SQuR+BFG4KZOwdD14afnjEMryzAFBesvMrpccIBQnjUcYLNkR gGBZ9sq8huIb38CqheZRep1+Dxy2FdL+ZsndXnA0oZtDmog60vTYhvopBci0IDFr 8LUBTzJSD/DelrEk8sfgm5Ot2+kzLiXruS18UywXk0glngoqUgaEaWDk0/9G1LfJ gOZK21rqJcyYQOCrNmADhuMrk0swBjwH7o/gZTPEMvFHYx8rg92yuoQVjBhmCQ5a itOfnj2FWHKKqxHLgoesjRFjh9vJZlAgwrjOaBPTy8w8Biy6dgPcYhr5k2MwXw/8 Vx6zoJ5bqefo1PK7rn6e709h5s+R0vUj+0z31Y4dQu59/GbXsG9UBBauyyfGCHOt N8uxo9rHVNDMISYeODr0xMrpygt2AF2QwXoHfl5wt+fbnk5Ra6aB0QC3kVe+ick/ e4zvkGnyKe4ARB45evkmec9Rc5UBSyUT4vRlUhzYUTK3QdzDZlYzIvqjB1xnrS4X TPjbBezvTVwqkb6cXQxoDdwfwyYIv0/ivgEQbEFpu9yr3+O1mN/AwxyLYehIgn/u TxIfXLwIpsuQhyuaCYNS =WI2p -----END PGP SIGNATURE----- --nLkN8UIJqRupMJFfrJOrroiVNW8CRLbMe--