From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36888) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yn7v0-0001tM-Mo for qemu-devel@nongnu.org; Tue, 28 Apr 2015 11:59:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yn7ux-0001Ef-Tm for qemu-devel@nongnu.org; Tue, 28 Apr 2015 11:59:30 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:13607) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yn7ux-0001EZ-Nl for qemu-devel@nongnu.org; Tue, 28 Apr 2015 11:59:27 -0400 Message-ID: <553FAE58.9010609@imgtec.com> Date: Tue, 28 Apr 2015 16:59:20 +0100 From: Leon Alrae MIME-Version: 1.0 References: <1430224874-18513-1-git-send-email-leon.alrae@imgtec.com> <1430224874-18513-3-git-send-email-leon.alrae@imgtec.com> <553F8C8E.2030706@imgtec.com> In-Reply-To: <553F8C8E.2030706@imgtec.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 2/7] target-mips: support Page Frame Number Extension field List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: James Hogan , qemu-devel@nongnu.org Cc: aurelien@aurel32.net Hi James, On 28/04/2015 14:35, James Hogan wrote: > > > On 28/04/15 13:41, Leon Alrae wrote: >> Update tlb->PFN to contain PFN concatenated with PFNX. PFNX is 0 if large >> physical address is not supported. >> >> Signed-off-by: Leon Alrae >> --- >> target-mips/op_helper.c | 32 ++++++++++++++++++++++++++------ >> 1 file changed, 26 insertions(+), 6 deletions(-) >> >> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c >> index c9a60bd..6bff927 100644 >> --- a/target-mips/op_helper.c >> +++ b/target-mips/op_helper.c >> @@ -1825,6 +1825,16 @@ static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first) >> } >> } >> >> +static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo) >> +{ >> +#if defined(TARGET_MIPS64) >> + return extract64(entrylo, 6, 54); >> +#else >> + return extract64(entrylo, 6, 24) | /* PFN */ >> + (extract64(entrylo, 32, 32) << 24); /* PFNX */ > > Where does the 32,32 come from? The PRA I have seems to imply that PFNX > starts at bit 30 and goes up to bit 54. This comes directly from MIPS32 PRA (I presume you are looking at MIPS64 PRA). Note that EntryLo.PFNX starts at bit 32 as there is 2-bit gap occupied by RI/XI (unlike MIPS64 where it starts at bit 30). Regards, Leon