From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36686) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YoDHX-0005tc-5B for qemu-devel@nongnu.org; Fri, 01 May 2015 11:55:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YoDHT-0006yA-Va for qemu-devel@nongnu.org; Fri, 01 May 2015 11:55:15 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:23040) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YoDHT-0006xb-Ps for qemu-devel@nongnu.org; Fri, 01 May 2015 11:55:11 -0400 Message-ID: <5543A1DC.4040303@imgtec.com> Date: Fri, 1 May 2015 16:55:08 +0100 From: Yongbok Kim MIME-Version: 1.0 References: <1430493868-21452-1-git-send-email-yongbok.kim@imgtec.com> <1430493868-21452-4-git-send-email-yongbok.kim@imgtec.com> In-Reply-To: Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 3/3] target-mips: Misaligned Memory Accesses for MSA List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Leon Alrae , QEMU Developers On 01/05/2015 16:43, Peter Maydell wrote: > On 1 May 2015 at 16:24, Yongbok Kim wrote: >> MIPS SIMD Architecture vector loads and stores require misalignment support. >> MSA Memory access should work as an atomic operation. Therefore, it has to >> check validity of all the addresses for the operation. >> >> Signed-off-by: Yongbok Kim >> --- >> target-mips/op_helper.c | 30 ++++++++++++++++++++++++++++++ >> 1 files changed, 30 insertions(+), 0 deletions(-) >> >> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c >> index dacc92b..89a7de6 100644 >> --- a/target-mips/op_helper.c >> +++ b/target-mips/op_helper.c >> @@ -3571,6 +3571,24 @@ FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status) >> /* Element-by-element access macros */ >> #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df)) >> >> +#if !defined(CONFIG_USER_ONLY) >> +static bool cpu_mips_validate_msa_block_access(CPUMIPSState *env, >> + target_ulong address, int df, int rw) >> +{ >> + int i; >> + for (i = 0; i < DF_ELEMENTS(df); i++) { >> + if (!cpu_mips_validate_access(env, address + (i << df), >> + address, (1 << df), rw)) { >> + CPUState *cs = CPU(mips_env_get_cpu(env)); >> + helper_raise_exception_err(env, cs->exception_index, >> + env->error_code); > I was wondering if this would get the correct PC in the exception > case, but we always call save_cpu_state() before calling the > msa_ld/st_df helpers, so it will. > > -- PMM Yes it does because of the save_cpu_state(). Actually I have considered to use cpu_restore_state() with GETRA() but it looks like using save_cpu_state() is quite common in the target-mips. It would be good such clean-up for all the cases in the future work. But this patch I would follow existing style for the consistency. Regards, Yongbok