From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Chen, Tiejun" <tiejun.chen@intel.com>
Subject: Re: [PATCH 1/3] xen/vt-d: need barriers to workaround
	CLFLUSH
Date: Mon, 04 May 2015 19:26:02 +0800
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To: "Tian, Kevin" <kevin.tian@intel.com>, Jan Beulich <JBeulich@suse.com>
Cc: "Zhang, Yang Z" <yang.z.zhang@intel.com>, "jinsong.liu@alibaba-inc.com" <jinsong.liu@alibaba-inc.com>, "xen-devel@lists.xen.org" <xen-devel@lists.xen.org>, "keir@xen.org" <keir@xen.org>, "andrew.cooper3@citrix.com" <andrew.cooper3@citrix.com>
List-Id: xen-devel@lists.xenproject.org

On 2015/5/4 18:52, Tian, Kevin wrote:
>> From: Jan Beulich [mailto:JBeulich@suse.com]
>> Sent: Monday, May 04, 2015 6:44 PM
>>
>>>>> On 04.05.15 at 12:39, <tiejun.chen@intel.com> wrote:
>>> On 2015/5/4 16:52, Jan Beulich wrote:
>>>>>>> On 04.05.15 at 04:16, <tiejun.chen@intel.com> wrote:
>>>>> --- a/xen/drivers/passthrough/vtd/x86/vtd.c
>>>>> +++ b/xen/drivers/passthrough/vtd/x86/vtd.c
>>>>> @@ -56,7 +56,9 @@ unsigned int get_cache_line_size(void)
>>>>>
>>>>>    void cacheline_flush(char * addr)
>>>>>    {
>>>>> +    mb();
>>>>>        clflush(addr);
>>>>> +    mb();
>>>>>    }
>>>>
>>>> I think the purpose of the flush is to force write back, not to evict
>>>> the cache line, and if so wmb() would appear to be sufficient. As
>>>> the SDM says that's not the case, a comment explaining why wmb()
>>>> is not sufficient would seem necessary. Plus in the description I
>>>
>>> Seems wmb() is not sufficient here.
>>>
>>> "CLFLUSH is only ordered by the MFENCE instruction. It is not guaranteed
>>> to be ordered by any other fencing, serializing or other CLFLUSH
>>> instruction."
>>
>> Right - that's what I said in the second sentence.
>>
>
> btw why do we need two fences here? Suppose we just care about
> writes before the flush point...
>

The first MFENCE guarantees all load/store visible before flush cache 
line. But the second MFENCE just makes sure CLFLUSH is not ordered by 
that ensuing load/store, right?

Thanks
Tiejun