From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH v4 0/3] Set SMMU s2 input-size based on p2m tables Date: Tue, 5 May 2015 14:45:41 +0100 Message-ID: <5548C985.1020204@citrix.com> References: <1430444419-11564-1-git-send-email-edgar.iglesias@gmail.com> <1430831867.2660.89.camel@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1430831867.2660.89.camel@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell , "Edgar E. Iglesias" Cc: edgar.iglesias@xilinx.com, tim@xen.org, xen-devel@lists.xen.org, julien.grall@citrix.com, stefano.stabellini@citrix.com, Suravee Suthikulpanit List-Id: xen-devel@lists.xenproject.org Hi Ian, On 05/05/15 14:17, Ian Campbell wrote: > On Fri, 2015-05-01 at 11:40 +1000, Edgar E. Iglesias wrote: >> From: "Edgar E. Iglesias" >> >> Hi, >> >> This is a fix for the issue I'm seeing on ZynqMP with missmatched >> setup of the SMMU and the shared p2m page-tables with the CPU. > > Looking back at previous conversations it seems like your SMMU handles > fewer input bits than the second stage of the regular MMU, is that > right? > > Is there an architectural constraint that bits(SMMU) <= bits(MMU-s2)? His problem is bits(MMU-s2) <= bits(SMMU). Although, we were talking about hardware where the bits(SMMU) <= bits(MMU-s2). I have Seattle in mind but I haven't yet feedback from Suravee (in CC). Suravee, do you have any input? Having the bits(SMMU) <= bits(MMU-s2) would restrict the P2M to use 40 bits. Anything above won't be accessible to DOM0 because of the 1:1 mapping. Regards, -- Julien Grall