diff for duplicates of <554A7DE5.6040406@gmail.com> diff --git a/a/1.txt b/N1/1.txt index a7db187..6194181 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -5,7 +5,7 @@ On 06/05/15 14:19, Maxime Ripard wrote: >> The Allwinner H3 is a home entertainment system oriented SoC with >> four Cortex-A7 cores and a Mali-400MP2 GPU. >> ->> Signed-off-by: Jens Kuske <jenskuske@gmail.com> +>> Signed-off-by: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> >> --- >> arch/arm/boot/dts/sun8i-h3.dtsi | 468 ++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 468 insertions(+) @@ -18,7 +18,7 @@ On 06/05/15 14:19, Maxime Ripard wrote: >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi >> @@ -0,0 +1,468 @@ >> +/* ->> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> +>> + * Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> >> + * >> + * This file is dual-licensed: you can use it either under the terms >> + * of the GPL or the X11 license, at your option. Note that this dual @@ -83,25 +83,25 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + #address-cells = <1>; >> + #size-cells = <0>; >> + ->> + cpu at 0 { +>> + cpu@0 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <0>; >> + }; >> + ->> + cpu at 1 { +>> + cpu@1 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <1>; >> + }; >> + ->> + cpu at 2 { +>> + cpu@2 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <2>; >> + }; >> + ->> + cpu at 3 { +>> + cpu@3 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <3>; @@ -131,7 +131,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "osc32k"; >> + }; >> + ->> + pll1: clk at 01c20000 { +>> + pll1: clk@01c20000 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun8i-a23-pll1-clk"; >> + reg = <0x01c20000 0x4>; @@ -139,7 +139,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "pll1"; >> + }; >> + ->> + pll6: clk at 01c20028 { +>> + pll6: clk@01c20028 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun8i-h3-pll6-clk"; >> + reg = <0x01c20028 0x4>; @@ -147,7 +147,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "pll6", "pll6x2", "pll6d2"; >> + }; >> + ->> + pll8: clk at 01c20044 { +>> + pll8: clk@01c20044 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun8i-h3-pll8-clk"; >> + reg = <0x01c20044 0x4>; @@ -155,7 +155,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "pll8"; >> + }; >> + ->> + cpu: cpu_clk at 01c20050 { +>> + cpu: cpu_clk@01c20050 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-cpu-clk"; >> + reg = <0x01c20050 0x4>; @@ -163,7 +163,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "cpu"; >> + }; >> + ->> + axi: axi_clk at 01c20050 { +>> + axi: axi_clk@01c20050 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-axi-clk"; >> + reg = <0x01c20050 0x4>; @@ -171,7 +171,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "axi"; >> + }; >> + ->> + ahb1: ahb1_clk at 01c20054 { +>> + ahb1: ahb1_clk@01c20054 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun6i-a31-ahb1-clk"; >> + reg = <0x01c20054 0x4>; @@ -179,7 +179,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "ahb1"; >> + }; >> + ->> + ahb2: ahb2_clk at 01c2005c { +>> + ahb2: ahb2_clk@01c2005c { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun8i-h3-ahb2-clk"; >> + reg = <0x01c2005c 0x4>; @@ -187,7 +187,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "ahb2"; >> + }; >> + ->> + apb1: apb1_clk at 01c20054 { +>> + apb1: apb1_clk@01c20054 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-apb0-clk"; >> + reg = <0x01c20054 0x4>; @@ -195,7 +195,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "apb1"; >> + }; >> + ->> + apb2: apb2_clk at 01c20058 { +>> + apb2: apb2_clk@01c20058 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-apb1-clk"; >> + reg = <0x01c20058 0x4>; @@ -203,7 +203,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "apb2"; >> + }; >> + ->> + ahb1_gates: ahb1_gates_clk at 01c20060 { +>> + ahb1_gates: ahb1_gates_clk@01c20060 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun8i-h3-ahb1-gates-clk"; >> + reg = <0x01c20060 0x14>; @@ -221,7 +221,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + "ahb1_spinlock", "ahb1_ephy", "ahb1_dbg"; >> + }; >> + ->> + ahb2_gates: ahb2_gates_clk at 01c20060 { +>> + ahb2_gates: ahb2_gates_clk@01c20060 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun8i-h3-ahb2-gates-clk"; >> + reg = <0x01c20060 0x4>; @@ -230,7 +230,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + "ahb2_ohic2", "ahb2_ohic3"; >> + }; >> + ->> + apb1_gates: clk at 01c20068 { +>> + apb1_gates: clk@01c20068 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun8i-h3-apb1-gates-clk"; >> + reg = <0x01c20068 0x4>; @@ -240,7 +240,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + "apb1_i2s1", "apb1_i2s2"; >> + }; >> + ->> + apb2_gates: clk at 01c2006c { +>> + apb2_gates: clk@01c2006c { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun8i-h3-apb2-gates-clk"; >> + reg = <0x01c2006c 0x4>; @@ -259,7 +259,7 @@ apb2_scr as mentioned in the pinctrl thread. > >> + }; >> + ->> + mmc0_clk: clk at 01c20088 { +>> + mmc0_clk: clk@01c20088 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> + reg = <0x01c20088 0x4>; @@ -269,7 +269,7 @@ apb2_scr as mentioned in the pinctrl thread. >> + "mmc0_sample"; >> + }; >> + ->> + mmc1_clk: clk at 01c2008c { +>> + mmc1_clk: clk@01c2008c { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> + reg = <0x01c2008c 0x4>; @@ -279,7 +279,7 @@ apb2_scr as mentioned in the pinctrl thread. >> + "mmc1_sample"; >> + }; >> + ->> + mmc2_clk: clk at 01c20090 { +>> + mmc2_clk: clk@01c20090 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> + reg = <0x01c20090 0x4>; @@ -290,13 +290,13 @@ apb2_scr as mentioned in the pinctrl thread. >> + }; >> + }; >> + ->> + soc at 01c00000 { +>> + soc@01c00000 { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + ->> + dma: dma-controller at 01c02000 { +>> + dma: dma-controller@01c02000 { >> + compatible = "allwinner,sun8i-h3-dma"; >> + reg = <0x01c02000 0x1000>; >> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; @@ -305,7 +305,7 @@ apb2_scr as mentioned in the pinctrl thread. >> + #dma-cells = <1>; >> + }; >> + ->> + mmc0: mmc at 01c0f000 { +>> + mmc0: mmc@01c0f000 { >> + compatible = "allwinner,sun5i-a13-mmc"; >> + reg = <0x01c0f000 0x1000>; >> + clocks = <&ahb1_gates 8>, @@ -322,7 +322,7 @@ apb2_scr as mentioned in the pinctrl thread. >> + status = "disabled"; >> + }; >> + ->> + mmc1: mmc at 01c10000 { +>> + mmc1: mmc@01c10000 { >> + compatible = "allwinner,sun5i-a13-mmc"; >> + reg = <0x01c10000 0x1000>; >> + clocks = <&ahb1_gates 9>, @@ -339,7 +339,7 @@ apb2_scr as mentioned in the pinctrl thread. >> + status = "disabled"; >> + }; >> + ->> + mmc2: mmc at 01c11000 { +>> + mmc2: mmc@01c11000 { >> + compatible = "allwinner,sun5i-a13-mmc"; >> + reg = <0x01c11000 0x1000>; >> + clocks = <&ahb1_gates 10>, @@ -356,7 +356,7 @@ apb2_scr as mentioned in the pinctrl thread. >> + status = "disabled"; >> + }; >> + ->> + pio: pinctrl at 01c20800 { +>> + pio: pinctrl@01c20800 { >> + compatible = "allwinner,sun8i-h3-pinctrl"; >> + reg = <0x01c20800 0x400>; >> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -368,14 +368,14 @@ apb2_scr as mentioned in the pinctrl thread. >> + #size-cells = <0>; >> + #gpio-cells = <3>; >> + ->> + uart0_pins_a: uart0 at 0 { +>> + uart0_pins_a: uart0@0 { >> + allwinner,pins = "PA4", "PA5"; >> + allwinner,function = "uart0"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + ->> + mmc0_pins_a: mmc0 at 0 { +>> + mmc0_pins_a: mmc0@0 { >> + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; > > Could you have spaces between the commas, and wrap the line at 80 @@ -388,14 +388,14 @@ ok >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + ->> + mmc0_cd_pin: mmc0_cd_pin at 0 { +>> + mmc0_cd_pin: mmc0_cd_pin@0 { >> + allwinner,pins = "PF6"; >> + allwinner,function = "gpio_in"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; >> + }; >> + ->> + mmc1_pins_a: mmc1 at 0 { +>> + mmc1_pins_a: mmc1@0 { >> + allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5"; >> + allwinner,function = "mmc1"; >> + allwinner,drive = <SUN4I_PINCTRL_30_MA>; @@ -403,7 +403,7 @@ ok >> + }; >> + }; >> + ->> + ahb12_rst: reset at 01c202c0 { +>> + ahb12_rst: reset@01c202c0 { >> + #reset-cells = <1>; >> + compatible = "allwinner,sun6i-a31-clock-reset"; >> + reg = <0x01c202c0 0xc>; @@ -429,19 +429,19 @@ identical, it got removed after your comment: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html > ->> + apb1_rst: reset at 01c202d0 { +>> + apb1_rst: reset@01c202d0 { >> + #reset-cells = <1>; >> + compatible = "allwinner,sun6i-a31-clock-reset"; >> + reg = <0x01c202d0 0x4>; >> + }; >> + ->> + apb2_rst: reset at 01c202d8 { +>> + apb2_rst: reset@01c202d8 { >> + #reset-cells = <1>; >> + compatible = "allwinner,sun6i-a31-clock-reset"; >> + reg = <0x01c202d8 0x4>; >> + }; >> + ->> + timer at 01c20c00 { +>> + timer@01c20c00 { >> + compatible = "allwinner,sun4i-a10-timer"; >> + reg = <0x01c20c00 0xa0>; >> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -449,13 +449,13 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html >> + clocks = <&osc24M>; >> + }; >> + ->> + wdt0: watchdog at 01c20ca0 { +>> + wdt0: watchdog@01c20ca0 { >> + compatible = "allwinner,sun6i-a31-wdt"; >> + reg = <0x01c20ca0 0x20>; >> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + ->> + uart0: serial at 01c28000 { +>> + uart0: serial@01c28000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28000 0x400>; >> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -468,7 +468,7 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html >> + status = "disabled"; >> + }; >> + ->> + uart1: serial at 01c28400 { +>> + uart1: serial@01c28400 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28400 0x400>; >> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -481,7 +481,7 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html >> + status = "disabled"; >> + }; >> + ->> + uart2: serial at 01c28800 { +>> + uart2: serial@01c28800 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28800 0x400>; >> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -494,7 +494,7 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html >> + status = "disabled"; >> + }; >> + ->> + uart3: serial at 01c28c00 { +>> + uart3: serial@01c28c00 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28c00 0x400>; >> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -507,7 +507,7 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html >> + status = "disabled"; >> + }; >> + ->> + gic: interrupt-controller at 01c81000 { +>> + gic: interrupt-controller@01c81000 { >> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; >> + reg = <0x01c81000 0x1000>, >> + <0x01c82000 0x1000>, @@ -518,7 +518,7 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html >> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; >> + }; >> + ->> + rtc: rtc at 01f00000 { +>> + rtc: rtc@01f00000 { >> + compatible = "allwinner,sun6i-a31-rtc"; >> + reg = <0x01f00000 0x54>; >> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, diff --git a/a/content_digest b/N1/content_digest index 14d7340..60b52e3 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,10 +1,20 @@ "ref\01430904693-1404-1-git-send-email-jenskuske@gmail.com\0" "ref\01430904693-1404-6-git-send-email-jenskuske@gmail.com\0" "ref\020150506121941.GD11057@lukather\0" - "From\0jenskuske@gmail.com (Jens Kuske)\0" - "Subject\0[PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI\0" + "From\0Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" + "Subject\0Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI\0" "Date\0Wed, 06 May 2015 22:47:33 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>\0" + "Cc\0Emilio L\303\263pez <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>" + Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + Vinod Koul <vinod.koul-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> + Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org\0" "\00:1\0" "b\0" "Hi,\n" @@ -14,7 +24,7 @@ ">> The Allwinner H3 is a home entertainment system oriented SoC with\n" ">> four Cortex-A7 cores and a Mali-400MP2 GPU.\n" ">>\n" - ">> Signed-off-by: Jens Kuske <jenskuske@gmail.com>\n" + ">> Signed-off-by: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" ">> ---\n" ">> arch/arm/boot/dts/sun8i-h3.dtsi | 468 ++++++++++++++++++++++++++++++++++++++++\n" ">> 1 file changed, 468 insertions(+)\n" @@ -27,7 +37,7 @@ ">> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi\n" ">> @@ -0,0 +1,468 @@\n" ">> +/*\n" - ">> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>\n" + ">> + * Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" ">> + *\n" ">> + * This file is dual-licensed: you can use it either under the terms\n" ">> + * of the GPL or the X11 license, at your option. Note that this dual\n" @@ -92,25 +102,25 @@ ">> +\t\t#address-cells = <1>;\n" ">> +\t\t#size-cells = <0>;\n" ">> +\n" - ">> +\t\tcpu at 0 {\n" + ">> +\t\tcpu@0 {\n" ">> +\t\t\tcompatible = \"arm,cortex-a7\";\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\treg = <0>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tcpu at 1 {\n" + ">> +\t\tcpu@1 {\n" ">> +\t\t\tcompatible = \"arm,cortex-a7\";\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\treg = <1>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tcpu at 2 {\n" + ">> +\t\tcpu@2 {\n" ">> +\t\t\tcompatible = \"arm,cortex-a7\";\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\treg = <2>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tcpu at 3 {\n" + ">> +\t\tcpu@3 {\n" ">> +\t\t\tcompatible = \"arm,cortex-a7\";\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\treg = <3>;\n" @@ -140,7 +150,7 @@ ">> +\t\t\tclock-output-names = \"osc32k\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tpll1: clk at 01c20000 {\n" + ">> +\t\tpll1: clk@01c20000 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n" ">> +\t\t\treg = <0x01c20000 0x4>;\n" @@ -148,7 +158,7 @@ ">> +\t\t\tclock-output-names = \"pll1\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tpll6: clk at 01c20028 {\n" + ">> +\t\tpll6: clk@01c20028 {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-pll6-clk\";\n" ">> +\t\t\treg = <0x01c20028 0x4>;\n" @@ -156,7 +166,7 @@ ">> +\t\t\tclock-output-names = \"pll6\", \"pll6x2\", \"pll6d2\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tpll8: clk at 01c20044 {\n" + ">> +\t\tpll8: clk@01c20044 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-pll8-clk\";\n" ">> +\t\t\treg = <0x01c20044 0x4>;\n" @@ -164,7 +174,7 @@ ">> +\t\t\tclock-output-names = \"pll8\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tcpu: cpu_clk at 01c20050 {\n" + ">> +\t\tcpu: cpu_clk@01c20050 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" ">> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -172,7 +182,7 @@ ">> +\t\t\tclock-output-names = \"cpu\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\taxi: axi_clk at 01c20050 {\n" + ">> +\t\taxi: axi_clk@01c20050 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-axi-clk\";\n" ">> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -180,7 +190,7 @@ ">> +\t\t\tclock-output-names = \"axi\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tahb1: ahb1_clk at 01c20054 {\n" + ">> +\t\tahb1: ahb1_clk@01c20054 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" ">> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -188,7 +198,7 @@ ">> +\t\t\tclock-output-names = \"ahb1\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tahb2: ahb2_clk at 01c2005c {\n" + ">> +\t\tahb2: ahb2_clk@01c2005c {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb2-clk\";\n" ">> +\t\t\treg = <0x01c2005c 0x4>;\n" @@ -196,7 +206,7 @@ ">> +\t\t\tclock-output-names = \"ahb2\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tapb1: apb1_clk at 01c20054 {\n" + ">> +\t\tapb1: apb1_clk@01c20054 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" ">> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -204,7 +214,7 @@ ">> +\t\t\tclock-output-names = \"apb1\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tapb2: apb2_clk at 01c20058 {\n" + ">> +\t\tapb2: apb2_clk@01c20058 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n" ">> +\t\t\treg = <0x01c20058 0x4>;\n" @@ -212,7 +222,7 @@ ">> +\t\t\tclock-output-names = \"apb2\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tahb1_gates: ahb1_gates_clk at 01c20060 {\n" + ">> +\t\tahb1_gates: ahb1_gates_clk@01c20060 {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb1-gates-clk\";\n" ">> +\t\t\treg = <0x01c20060 0x14>;\n" @@ -230,7 +240,7 @@ ">> +\t\t\t\t\t\"ahb1_spinlock\", \"ahb1_ephy\", \"ahb1_dbg\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tahb2_gates: ahb2_gates_clk at 01c20060 {\n" + ">> +\t\tahb2_gates: ahb2_gates_clk@01c20060 {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb2-gates-clk\";\n" ">> +\t\t\treg = <0x01c20060 0x4>;\n" @@ -239,7 +249,7 @@ ">> +\t\t\t\t\t\"ahb2_ohic2\", \"ahb2_ohic3\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tapb1_gates: clk at 01c20068 {\n" + ">> +\t\tapb1_gates: clk@01c20068 {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-apb1-gates-clk\";\n" ">> +\t\t\treg = <0x01c20068 0x4>;\n" @@ -249,7 +259,7 @@ ">> +\t\t\t\t\t\"apb1_i2s1\", \"apb1_i2s2\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tapb2_gates: clk at 01c2006c {\n" + ">> +\t\tapb2_gates: clk@01c2006c {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-apb2-gates-clk\";\n" ">> +\t\t\treg = <0x01c2006c 0x4>;\n" @@ -268,7 +278,7 @@ "> \n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tmmc0_clk: clk at 01c20088 {\n" + ">> +\t\tmmc0_clk: clk@01c20088 {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">> +\t\t\treg = <0x01c20088 0x4>;\n" @@ -278,7 +288,7 @@ ">> +\t\t\t\t\t \"mmc0_sample\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tmmc1_clk: clk at 01c2008c {\n" + ">> +\t\tmmc1_clk: clk@01c2008c {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">> +\t\t\treg = <0x01c2008c 0x4>;\n" @@ -288,7 +298,7 @@ ">> +\t\t\t\t\t \"mmc1_sample\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tmmc2_clk: clk at 01c20090 {\n" + ">> +\t\tmmc2_clk: clk@01c20090 {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">> +\t\t\treg = <0x01c20090 0x4>;\n" @@ -299,13 +309,13 @@ ">> +\t\t};\n" ">> +\t};\n" ">> +\n" - ">> +\tsoc at 01c00000 {\n" + ">> +\tsoc@01c00000 {\n" ">> +\t\tcompatible = \"simple-bus\";\n" ">> +\t\t#address-cells = <1>;\n" ">> +\t\t#size-cells = <1>;\n" ">> +\t\tranges;\n" ">> +\n" - ">> +\t\tdma: dma-controller at 01c02000 {\n" + ">> +\t\tdma: dma-controller@01c02000 {\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-dma\";\n" ">> +\t\t\treg = <0x01c02000 0x1000>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -314,7 +324,7 @@ ">> +\t\t\t#dma-cells = <1>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tmmc0: mmc at 01c0f000 {\n" + ">> +\t\tmmc0: mmc@01c0f000 {\n" ">> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" ">> +\t\t\treg = <0x01c0f000 0x1000>;\n" ">> +\t\t\tclocks = <&ahb1_gates 8>,\n" @@ -331,7 +341,7 @@ ">> +\t\t\tstatus = \"disabled\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tmmc1: mmc at 01c10000 {\n" + ">> +\t\tmmc1: mmc@01c10000 {\n" ">> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" ">> +\t\t\treg = <0x01c10000 0x1000>;\n" ">> +\t\t\tclocks = <&ahb1_gates 9>,\n" @@ -348,7 +358,7 @@ ">> +\t\t\tstatus = \"disabled\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tmmc2: mmc at 01c11000 {\n" + ">> +\t\tmmc2: mmc@01c11000 {\n" ">> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" ">> +\t\t\treg = <0x01c11000 0x1000>;\n" ">> +\t\t\tclocks = <&ahb1_gates 10>,\n" @@ -365,7 +375,7 @@ ">> +\t\t\tstatus = \"disabled\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tpio: pinctrl at 01c20800 {\n" + ">> +\t\tpio: pinctrl@01c20800 {\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-pinctrl\";\n" ">> +\t\t\treg = <0x01c20800 0x400>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -377,14 +387,14 @@ ">> +\t\t\t#size-cells = <0>;\n" ">> +\t\t\t#gpio-cells = <3>;\n" ">> +\n" - ">> +\t\t\tuart0_pins_a: uart0 at 0 {\n" + ">> +\t\t\tuart0_pins_a: uart0@0 {\n" ">> +\t\t\t\tallwinner,pins = \"PA4\", \"PA5\";\n" ">> +\t\t\t\tallwinner,function = \"uart0\";\n" ">> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" ">> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">> +\t\t\t};\n" ">> +\n" - ">> +\t\t\tmmc0_pins_a: mmc0 at 0 {\n" + ">> +\t\t\tmmc0_pins_a: mmc0@0 {\n" ">> +\t\t\t\tallwinner,pins = \"PF0\",\"PF1\",\"PF2\",\"PF3\",\"PF4\",\"PF5\";\n" "> \n" "> Could you have spaces between the commas, and wrap the line at 80\n" @@ -397,14 +407,14 @@ ">> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">> +\t\t\t};\n" ">> +\n" - ">> +\t\t\tmmc0_cd_pin: mmc0_cd_pin at 0 {\n" + ">> +\t\t\tmmc0_cd_pin: mmc0_cd_pin@0 {\n" ">> +\t\t\t\tallwinner,pins = \"PF6\";\n" ">> +\t\t\t\tallwinner,function = \"gpio_in\";\n" ">> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" ">> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_PULL_UP>;\n" ">> +\t\t\t};\n" ">> +\n" - ">> +\t\t\tmmc1_pins_a: mmc1 at 0 {\n" + ">> +\t\t\tmmc1_pins_a: mmc1@0 {\n" ">> +\t\t\t\tallwinner,pins = \"PG0\",\"PG1\",\"PG2\",\"PG3\",\"PG4\",\"PG5\";\n" ">> +\t\t\t\tallwinner,function = \"mmc1\";\n" ">> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n" @@ -412,7 +422,7 @@ ">> +\t\t\t};\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tahb12_rst: reset at 01c202c0 {\n" + ">> +\t\tahb12_rst: reset@01c202c0 {\n" ">> +\t\t\t#reset-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" ">> +\t\t\treg = <0x01c202c0 0xc>;\n" @@ -438,19 +448,19 @@ "http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html\n" "\n" "> \n" - ">> +\t\tapb1_rst: reset at 01c202d0 {\n" + ">> +\t\tapb1_rst: reset@01c202d0 {\n" ">> +\t\t\t#reset-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" ">> +\t\t\treg = <0x01c202d0 0x4>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tapb2_rst: reset at 01c202d8 {\n" + ">> +\t\tapb2_rst: reset@01c202d8 {\n" ">> +\t\t\t#reset-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" ">> +\t\t\treg = <0x01c202d8 0x4>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\ttimer at 01c20c00 {\n" + ">> +\t\ttimer@01c20c00 {\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-timer\";\n" ">> +\t\t\treg = <0x01c20c00 0xa0>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -458,13 +468,13 @@ ">> +\t\t\tclocks = <&osc24M>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\twdt0: watchdog at 01c20ca0 {\n" + ">> +\t\twdt0: watchdog@01c20ca0 {\n" ">> +\t\t\tcompatible = \"allwinner,sun6i-a31-wdt\";\n" ">> +\t\t\treg = <0x01c20ca0 0x20>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tuart0: serial at 01c28000 {\n" + ">> +\t\tuart0: serial@01c28000 {\n" ">> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" ">> +\t\t\treg = <0x01c28000 0x400>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -477,7 +487,7 @@ ">> +\t\t\tstatus = \"disabled\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tuart1: serial at 01c28400 {\n" + ">> +\t\tuart1: serial@01c28400 {\n" ">> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" ">> +\t\t\treg = <0x01c28400 0x400>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -490,7 +500,7 @@ ">> +\t\t\tstatus = \"disabled\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tuart2: serial at 01c28800 {\n" + ">> +\t\tuart2: serial@01c28800 {\n" ">> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" ">> +\t\t\treg = <0x01c28800 0x400>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -503,7 +513,7 @@ ">> +\t\t\tstatus = \"disabled\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tuart3: serial at 01c28c00 {\n" + ">> +\t\tuart3: serial@01c28c00 {\n" ">> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" ">> +\t\t\treg = <0x01c28c00 0x400>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -516,7 +526,7 @@ ">> +\t\t\tstatus = \"disabled\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tgic: interrupt-controller at 01c81000 {\n" + ">> +\t\tgic: interrupt-controller@01c81000 {\n" ">> +\t\t\tcompatible = \"arm,cortex-a7-gic\", \"arm,cortex-a15-gic\";\n" ">> +\t\t\treg = <0x01c81000 0x1000>,\n" ">> +\t\t\t <0x01c82000 0x1000>,\n" @@ -527,7 +537,7 @@ ">> +\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\trtc: rtc at 01f00000 {\n" + ">> +\t\trtc: rtc@01f00000 {\n" ">> +\t\t\tcompatible = \"allwinner,sun6i-a31-rtc\";\n" ">> +\t\t\treg = <0x01f00000 0x54>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -545,4 +555,4 @@ "\n" Jens -dede3b8c8080fd19629fcd3482baeab23c0a8488ddb167ccf3ef1bff04bd8965 +7a6e6c72898d396e6f612a5c64d03fa3001224493c8df7bd4e94078c2a3f7590
diff --git a/a/1.txt b/N2/1.txt index a7db187..7bd0db9 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -83,25 +83,25 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + #address-cells = <1>; >> + #size-cells = <0>; >> + ->> + cpu at 0 { +>> + cpu@0 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <0>; >> + }; >> + ->> + cpu at 1 { +>> + cpu@1 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <1>; >> + }; >> + ->> + cpu at 2 { +>> + cpu@2 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <2>; >> + }; >> + ->> + cpu at 3 { +>> + cpu@3 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <3>; @@ -131,7 +131,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "osc32k"; >> + }; >> + ->> + pll1: clk at 01c20000 { +>> + pll1: clk@01c20000 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun8i-a23-pll1-clk"; >> + reg = <0x01c20000 0x4>; @@ -139,7 +139,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "pll1"; >> + }; >> + ->> + pll6: clk at 01c20028 { +>> + pll6: clk@01c20028 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun8i-h3-pll6-clk"; >> + reg = <0x01c20028 0x4>; @@ -147,7 +147,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "pll6", "pll6x2", "pll6d2"; >> + }; >> + ->> + pll8: clk at 01c20044 { +>> + pll8: clk@01c20044 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun8i-h3-pll8-clk"; >> + reg = <0x01c20044 0x4>; @@ -155,7 +155,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "pll8"; >> + }; >> + ->> + cpu: cpu_clk at 01c20050 { +>> + cpu: cpu_clk@01c20050 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-cpu-clk"; >> + reg = <0x01c20050 0x4>; @@ -163,7 +163,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "cpu"; >> + }; >> + ->> + axi: axi_clk at 01c20050 { +>> + axi: axi_clk@01c20050 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-axi-clk"; >> + reg = <0x01c20050 0x4>; @@ -171,7 +171,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "axi"; >> + }; >> + ->> + ahb1: ahb1_clk at 01c20054 { +>> + ahb1: ahb1_clk@01c20054 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun6i-a31-ahb1-clk"; >> + reg = <0x01c20054 0x4>; @@ -179,7 +179,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "ahb1"; >> + }; >> + ->> + ahb2: ahb2_clk at 01c2005c { +>> + ahb2: ahb2_clk@01c2005c { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun8i-h3-ahb2-clk"; >> + reg = <0x01c2005c 0x4>; @@ -187,7 +187,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "ahb2"; >> + }; >> + ->> + apb1: apb1_clk at 01c20054 { +>> + apb1: apb1_clk@01c20054 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-apb0-clk"; >> + reg = <0x01c20054 0x4>; @@ -195,7 +195,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "apb1"; >> + }; >> + ->> + apb2: apb2_clk at 01c20058 { +>> + apb2: apb2_clk@01c20058 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-apb1-clk"; >> + reg = <0x01c20058 0x4>; @@ -203,7 +203,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + clock-output-names = "apb2"; >> + }; >> + ->> + ahb1_gates: ahb1_gates_clk at 01c20060 { +>> + ahb1_gates: ahb1_gates_clk@01c20060 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun8i-h3-ahb1-gates-clk"; >> + reg = <0x01c20060 0x14>; @@ -221,7 +221,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + "ahb1_spinlock", "ahb1_ephy", "ahb1_dbg"; >> + }; >> + ->> + ahb2_gates: ahb2_gates_clk at 01c20060 { +>> + ahb2_gates: ahb2_gates_clk@01c20060 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun8i-h3-ahb2-gates-clk"; >> + reg = <0x01c20060 0x4>; @@ -230,7 +230,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + "ahb2_ohic2", "ahb2_ohic3"; >> + }; >> + ->> + apb1_gates: clk at 01c20068 { +>> + apb1_gates: clk@01c20068 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun8i-h3-apb1-gates-clk"; >> + reg = <0x01c20068 0x4>; @@ -240,7 +240,7 @@ Sure, will be removed. Just copied it from some other sunxi dtsi. >> + "apb1_i2s1", "apb1_i2s2"; >> + }; >> + ->> + apb2_gates: clk at 01c2006c { +>> + apb2_gates: clk@01c2006c { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun8i-h3-apb2-gates-clk"; >> + reg = <0x01c2006c 0x4>; @@ -259,7 +259,7 @@ apb2_scr as mentioned in the pinctrl thread. > >> + }; >> + ->> + mmc0_clk: clk at 01c20088 { +>> + mmc0_clk: clk@01c20088 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> + reg = <0x01c20088 0x4>; @@ -269,7 +269,7 @@ apb2_scr as mentioned in the pinctrl thread. >> + "mmc0_sample"; >> + }; >> + ->> + mmc1_clk: clk at 01c2008c { +>> + mmc1_clk: clk@01c2008c { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> + reg = <0x01c2008c 0x4>; @@ -279,7 +279,7 @@ apb2_scr as mentioned in the pinctrl thread. >> + "mmc1_sample"; >> + }; >> + ->> + mmc2_clk: clk at 01c20090 { +>> + mmc2_clk: clk@01c20090 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> + reg = <0x01c20090 0x4>; @@ -290,13 +290,13 @@ apb2_scr as mentioned in the pinctrl thread. >> + }; >> + }; >> + ->> + soc at 01c00000 { +>> + soc@01c00000 { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + ->> + dma: dma-controller at 01c02000 { +>> + dma: dma-controller@01c02000 { >> + compatible = "allwinner,sun8i-h3-dma"; >> + reg = <0x01c02000 0x1000>; >> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; @@ -305,7 +305,7 @@ apb2_scr as mentioned in the pinctrl thread. >> + #dma-cells = <1>; >> + }; >> + ->> + mmc0: mmc at 01c0f000 { +>> + mmc0: mmc@01c0f000 { >> + compatible = "allwinner,sun5i-a13-mmc"; >> + reg = <0x01c0f000 0x1000>; >> + clocks = <&ahb1_gates 8>, @@ -322,7 +322,7 @@ apb2_scr as mentioned in the pinctrl thread. >> + status = "disabled"; >> + }; >> + ->> + mmc1: mmc at 01c10000 { +>> + mmc1: mmc@01c10000 { >> + compatible = "allwinner,sun5i-a13-mmc"; >> + reg = <0x01c10000 0x1000>; >> + clocks = <&ahb1_gates 9>, @@ -339,7 +339,7 @@ apb2_scr as mentioned in the pinctrl thread. >> + status = "disabled"; >> + }; >> + ->> + mmc2: mmc at 01c11000 { +>> + mmc2: mmc@01c11000 { >> + compatible = "allwinner,sun5i-a13-mmc"; >> + reg = <0x01c11000 0x1000>; >> + clocks = <&ahb1_gates 10>, @@ -356,7 +356,7 @@ apb2_scr as mentioned in the pinctrl thread. >> + status = "disabled"; >> + }; >> + ->> + pio: pinctrl at 01c20800 { +>> + pio: pinctrl@01c20800 { >> + compatible = "allwinner,sun8i-h3-pinctrl"; >> + reg = <0x01c20800 0x400>; >> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -368,14 +368,14 @@ apb2_scr as mentioned in the pinctrl thread. >> + #size-cells = <0>; >> + #gpio-cells = <3>; >> + ->> + uart0_pins_a: uart0 at 0 { +>> + uart0_pins_a: uart0@0 { >> + allwinner,pins = "PA4", "PA5"; >> + allwinner,function = "uart0"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + ->> + mmc0_pins_a: mmc0 at 0 { +>> + mmc0_pins_a: mmc0@0 { >> + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; > > Could you have spaces between the commas, and wrap the line at 80 @@ -388,14 +388,14 @@ ok >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + ->> + mmc0_cd_pin: mmc0_cd_pin at 0 { +>> + mmc0_cd_pin: mmc0_cd_pin@0 { >> + allwinner,pins = "PF6"; >> + allwinner,function = "gpio_in"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; >> + }; >> + ->> + mmc1_pins_a: mmc1 at 0 { +>> + mmc1_pins_a: mmc1@0 { >> + allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5"; >> + allwinner,function = "mmc1"; >> + allwinner,drive = <SUN4I_PINCTRL_30_MA>; @@ -403,7 +403,7 @@ ok >> + }; >> + }; >> + ->> + ahb12_rst: reset at 01c202c0 { +>> + ahb12_rst: reset@01c202c0 { >> + #reset-cells = <1>; >> + compatible = "allwinner,sun6i-a31-clock-reset"; >> + reg = <0x01c202c0 0xc>; @@ -429,19 +429,19 @@ identical, it got removed after your comment: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html > ->> + apb1_rst: reset at 01c202d0 { +>> + apb1_rst: reset@01c202d0 { >> + #reset-cells = <1>; >> + compatible = "allwinner,sun6i-a31-clock-reset"; >> + reg = <0x01c202d0 0x4>; >> + }; >> + ->> + apb2_rst: reset at 01c202d8 { +>> + apb2_rst: reset@01c202d8 { >> + #reset-cells = <1>; >> + compatible = "allwinner,sun6i-a31-clock-reset"; >> + reg = <0x01c202d8 0x4>; >> + }; >> + ->> + timer at 01c20c00 { +>> + timer@01c20c00 { >> + compatible = "allwinner,sun4i-a10-timer"; >> + reg = <0x01c20c00 0xa0>; >> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -449,13 +449,13 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html >> + clocks = <&osc24M>; >> + }; >> + ->> + wdt0: watchdog at 01c20ca0 { +>> + wdt0: watchdog@01c20ca0 { >> + compatible = "allwinner,sun6i-a31-wdt"; >> + reg = <0x01c20ca0 0x20>; >> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + ->> + uart0: serial at 01c28000 { +>> + uart0: serial@01c28000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28000 0x400>; >> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -468,7 +468,7 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html >> + status = "disabled"; >> + }; >> + ->> + uart1: serial at 01c28400 { +>> + uart1: serial@01c28400 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28400 0x400>; >> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -481,7 +481,7 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html >> + status = "disabled"; >> + }; >> + ->> + uart2: serial at 01c28800 { +>> + uart2: serial@01c28800 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28800 0x400>; >> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -494,7 +494,7 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html >> + status = "disabled"; >> + }; >> + ->> + uart3: serial at 01c28c00 { +>> + uart3: serial@01c28c00 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28c00 0x400>; >> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -507,7 +507,7 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html >> + status = "disabled"; >> + }; >> + ->> + gic: interrupt-controller at 01c81000 { +>> + gic: interrupt-controller@01c81000 { >> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; >> + reg = <0x01c81000 0x1000>, >> + <0x01c82000 0x1000>, @@ -518,7 +518,7 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html >> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; >> + }; >> + ->> + rtc: rtc at 01f00000 { +>> + rtc: rtc@01f00000 { >> + compatible = "allwinner,sun6i-a31-rtc"; >> + reg = <0x01f00000 0x54>; >> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, diff --git a/a/content_digest b/N2/content_digest index 14d7340..3a24480 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,10 +1,20 @@ "ref\01430904693-1404-1-git-send-email-jenskuske@gmail.com\0" "ref\01430904693-1404-6-git-send-email-jenskuske@gmail.com\0" "ref\020150506121941.GD11057@lukather\0" - "From\0jenskuske@gmail.com (Jens Kuske)\0" - "Subject\0[PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI\0" + "From\0Jens Kuske <jenskuske@gmail.com>\0" + "Subject\0Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI\0" "Date\0Wed, 06 May 2015 22:47:33 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Maxime Ripard <maxime.ripard@free-electrons.com>\0" + "Cc\0Emilio L\303\263pez <emilio@elopez.com.ar>" + Mike Turquette <mturquette@linaro.org> + Linus Walleij <linus.walleij@linaro.org> + Vinod Koul <vinod.koul@intel.com> + Rob Herring <robh+dt@kernel.org> + Chen-Yu Tsai <wens@csie.org> + devicetree@vger.kernel.org + linux-arm-kernel@lists.infradead.org + linux-kernel@vger.kernel.org + " linux-sunxi@googlegroups.com\0" "\00:1\0" "b\0" "Hi,\n" @@ -92,25 +102,25 @@ ">> +\t\t#address-cells = <1>;\n" ">> +\t\t#size-cells = <0>;\n" ">> +\n" - ">> +\t\tcpu at 0 {\n" + ">> +\t\tcpu@0 {\n" ">> +\t\t\tcompatible = \"arm,cortex-a7\";\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\treg = <0>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tcpu at 1 {\n" + ">> +\t\tcpu@1 {\n" ">> +\t\t\tcompatible = \"arm,cortex-a7\";\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\treg = <1>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tcpu at 2 {\n" + ">> +\t\tcpu@2 {\n" ">> +\t\t\tcompatible = \"arm,cortex-a7\";\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\treg = <2>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tcpu at 3 {\n" + ">> +\t\tcpu@3 {\n" ">> +\t\t\tcompatible = \"arm,cortex-a7\";\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\treg = <3>;\n" @@ -140,7 +150,7 @@ ">> +\t\t\tclock-output-names = \"osc32k\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tpll1: clk at 01c20000 {\n" + ">> +\t\tpll1: clk@01c20000 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n" ">> +\t\t\treg = <0x01c20000 0x4>;\n" @@ -148,7 +158,7 @@ ">> +\t\t\tclock-output-names = \"pll1\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tpll6: clk at 01c20028 {\n" + ">> +\t\tpll6: clk@01c20028 {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-pll6-clk\";\n" ">> +\t\t\treg = <0x01c20028 0x4>;\n" @@ -156,7 +166,7 @@ ">> +\t\t\tclock-output-names = \"pll6\", \"pll6x2\", \"pll6d2\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tpll8: clk at 01c20044 {\n" + ">> +\t\tpll8: clk@01c20044 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-pll8-clk\";\n" ">> +\t\t\treg = <0x01c20044 0x4>;\n" @@ -164,7 +174,7 @@ ">> +\t\t\tclock-output-names = \"pll8\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tcpu: cpu_clk at 01c20050 {\n" + ">> +\t\tcpu: cpu_clk@01c20050 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" ">> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -172,7 +182,7 @@ ">> +\t\t\tclock-output-names = \"cpu\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\taxi: axi_clk at 01c20050 {\n" + ">> +\t\taxi: axi_clk@01c20050 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-axi-clk\";\n" ">> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -180,7 +190,7 @@ ">> +\t\t\tclock-output-names = \"axi\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tahb1: ahb1_clk at 01c20054 {\n" + ">> +\t\tahb1: ahb1_clk@01c20054 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" ">> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -188,7 +198,7 @@ ">> +\t\t\tclock-output-names = \"ahb1\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tahb2: ahb2_clk at 01c2005c {\n" + ">> +\t\tahb2: ahb2_clk@01c2005c {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb2-clk\";\n" ">> +\t\t\treg = <0x01c2005c 0x4>;\n" @@ -196,7 +206,7 @@ ">> +\t\t\tclock-output-names = \"ahb2\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tapb1: apb1_clk at 01c20054 {\n" + ">> +\t\tapb1: apb1_clk@01c20054 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" ">> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -204,7 +214,7 @@ ">> +\t\t\tclock-output-names = \"apb1\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tapb2: apb2_clk at 01c20058 {\n" + ">> +\t\tapb2: apb2_clk@01c20058 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n" ">> +\t\t\treg = <0x01c20058 0x4>;\n" @@ -212,7 +222,7 @@ ">> +\t\t\tclock-output-names = \"apb2\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tahb1_gates: ahb1_gates_clk at 01c20060 {\n" + ">> +\t\tahb1_gates: ahb1_gates_clk@01c20060 {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb1-gates-clk\";\n" ">> +\t\t\treg = <0x01c20060 0x14>;\n" @@ -230,7 +240,7 @@ ">> +\t\t\t\t\t\"ahb1_spinlock\", \"ahb1_ephy\", \"ahb1_dbg\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tahb2_gates: ahb2_gates_clk at 01c20060 {\n" + ">> +\t\tahb2_gates: ahb2_gates_clk@01c20060 {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb2-gates-clk\";\n" ">> +\t\t\treg = <0x01c20060 0x4>;\n" @@ -239,7 +249,7 @@ ">> +\t\t\t\t\t\"ahb2_ohic2\", \"ahb2_ohic3\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tapb1_gates: clk at 01c20068 {\n" + ">> +\t\tapb1_gates: clk@01c20068 {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-apb1-gates-clk\";\n" ">> +\t\t\treg = <0x01c20068 0x4>;\n" @@ -249,7 +259,7 @@ ">> +\t\t\t\t\t\"apb1_i2s1\", \"apb1_i2s2\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tapb2_gates: clk at 01c2006c {\n" + ">> +\t\tapb2_gates: clk@01c2006c {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-apb2-gates-clk\";\n" ">> +\t\t\treg = <0x01c2006c 0x4>;\n" @@ -268,7 +278,7 @@ "> \n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tmmc0_clk: clk at 01c20088 {\n" + ">> +\t\tmmc0_clk: clk@01c20088 {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">> +\t\t\treg = <0x01c20088 0x4>;\n" @@ -278,7 +288,7 @@ ">> +\t\t\t\t\t \"mmc0_sample\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tmmc1_clk: clk at 01c2008c {\n" + ">> +\t\tmmc1_clk: clk@01c2008c {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">> +\t\t\treg = <0x01c2008c 0x4>;\n" @@ -288,7 +298,7 @@ ">> +\t\t\t\t\t \"mmc1_sample\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tmmc2_clk: clk at 01c20090 {\n" + ">> +\t\tmmc2_clk: clk@01c20090 {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">> +\t\t\treg = <0x01c20090 0x4>;\n" @@ -299,13 +309,13 @@ ">> +\t\t};\n" ">> +\t};\n" ">> +\n" - ">> +\tsoc at 01c00000 {\n" + ">> +\tsoc@01c00000 {\n" ">> +\t\tcompatible = \"simple-bus\";\n" ">> +\t\t#address-cells = <1>;\n" ">> +\t\t#size-cells = <1>;\n" ">> +\t\tranges;\n" ">> +\n" - ">> +\t\tdma: dma-controller at 01c02000 {\n" + ">> +\t\tdma: dma-controller@01c02000 {\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-dma\";\n" ">> +\t\t\treg = <0x01c02000 0x1000>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -314,7 +324,7 @@ ">> +\t\t\t#dma-cells = <1>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tmmc0: mmc at 01c0f000 {\n" + ">> +\t\tmmc0: mmc@01c0f000 {\n" ">> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" ">> +\t\t\treg = <0x01c0f000 0x1000>;\n" ">> +\t\t\tclocks = <&ahb1_gates 8>,\n" @@ -331,7 +341,7 @@ ">> +\t\t\tstatus = \"disabled\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tmmc1: mmc at 01c10000 {\n" + ">> +\t\tmmc1: mmc@01c10000 {\n" ">> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" ">> +\t\t\treg = <0x01c10000 0x1000>;\n" ">> +\t\t\tclocks = <&ahb1_gates 9>,\n" @@ -348,7 +358,7 @@ ">> +\t\t\tstatus = \"disabled\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tmmc2: mmc at 01c11000 {\n" + ">> +\t\tmmc2: mmc@01c11000 {\n" ">> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" ">> +\t\t\treg = <0x01c11000 0x1000>;\n" ">> +\t\t\tclocks = <&ahb1_gates 10>,\n" @@ -365,7 +375,7 @@ ">> +\t\t\tstatus = \"disabled\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tpio: pinctrl at 01c20800 {\n" + ">> +\t\tpio: pinctrl@01c20800 {\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-pinctrl\";\n" ">> +\t\t\treg = <0x01c20800 0x400>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -377,14 +387,14 @@ ">> +\t\t\t#size-cells = <0>;\n" ">> +\t\t\t#gpio-cells = <3>;\n" ">> +\n" - ">> +\t\t\tuart0_pins_a: uart0 at 0 {\n" + ">> +\t\t\tuart0_pins_a: uart0@0 {\n" ">> +\t\t\t\tallwinner,pins = \"PA4\", \"PA5\";\n" ">> +\t\t\t\tallwinner,function = \"uart0\";\n" ">> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" ">> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">> +\t\t\t};\n" ">> +\n" - ">> +\t\t\tmmc0_pins_a: mmc0 at 0 {\n" + ">> +\t\t\tmmc0_pins_a: mmc0@0 {\n" ">> +\t\t\t\tallwinner,pins = \"PF0\",\"PF1\",\"PF2\",\"PF3\",\"PF4\",\"PF5\";\n" "> \n" "> Could you have spaces between the commas, and wrap the line at 80\n" @@ -397,14 +407,14 @@ ">> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">> +\t\t\t};\n" ">> +\n" - ">> +\t\t\tmmc0_cd_pin: mmc0_cd_pin at 0 {\n" + ">> +\t\t\tmmc0_cd_pin: mmc0_cd_pin@0 {\n" ">> +\t\t\t\tallwinner,pins = \"PF6\";\n" ">> +\t\t\t\tallwinner,function = \"gpio_in\";\n" ">> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" ">> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_PULL_UP>;\n" ">> +\t\t\t};\n" ">> +\n" - ">> +\t\t\tmmc1_pins_a: mmc1 at 0 {\n" + ">> +\t\t\tmmc1_pins_a: mmc1@0 {\n" ">> +\t\t\t\tallwinner,pins = \"PG0\",\"PG1\",\"PG2\",\"PG3\",\"PG4\",\"PG5\";\n" ">> +\t\t\t\tallwinner,function = \"mmc1\";\n" ">> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n" @@ -412,7 +422,7 @@ ">> +\t\t\t};\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tahb12_rst: reset at 01c202c0 {\n" + ">> +\t\tahb12_rst: reset@01c202c0 {\n" ">> +\t\t\t#reset-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" ">> +\t\t\treg = <0x01c202c0 0xc>;\n" @@ -438,19 +448,19 @@ "http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html\n" "\n" "> \n" - ">> +\t\tapb1_rst: reset at 01c202d0 {\n" + ">> +\t\tapb1_rst: reset@01c202d0 {\n" ">> +\t\t\t#reset-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" ">> +\t\t\treg = <0x01c202d0 0x4>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tapb2_rst: reset at 01c202d8 {\n" + ">> +\t\tapb2_rst: reset@01c202d8 {\n" ">> +\t\t\t#reset-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" ">> +\t\t\treg = <0x01c202d8 0x4>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\ttimer at 01c20c00 {\n" + ">> +\t\ttimer@01c20c00 {\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-timer\";\n" ">> +\t\t\treg = <0x01c20c00 0xa0>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -458,13 +468,13 @@ ">> +\t\t\tclocks = <&osc24M>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\twdt0: watchdog at 01c20ca0 {\n" + ">> +\t\twdt0: watchdog@01c20ca0 {\n" ">> +\t\t\tcompatible = \"allwinner,sun6i-a31-wdt\";\n" ">> +\t\t\treg = <0x01c20ca0 0x20>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tuart0: serial at 01c28000 {\n" + ">> +\t\tuart0: serial@01c28000 {\n" ">> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" ">> +\t\t\treg = <0x01c28000 0x400>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -477,7 +487,7 @@ ">> +\t\t\tstatus = \"disabled\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tuart1: serial at 01c28400 {\n" + ">> +\t\tuart1: serial@01c28400 {\n" ">> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" ">> +\t\t\treg = <0x01c28400 0x400>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -490,7 +500,7 @@ ">> +\t\t\tstatus = \"disabled\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tuart2: serial at 01c28800 {\n" + ">> +\t\tuart2: serial@01c28800 {\n" ">> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" ">> +\t\t\treg = <0x01c28800 0x400>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -503,7 +513,7 @@ ">> +\t\t\tstatus = \"disabled\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tuart3: serial at 01c28c00 {\n" + ">> +\t\tuart3: serial@01c28c00 {\n" ">> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" ">> +\t\t\treg = <0x01c28c00 0x400>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -516,7 +526,7 @@ ">> +\t\t\tstatus = \"disabled\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tgic: interrupt-controller at 01c81000 {\n" + ">> +\t\tgic: interrupt-controller@01c81000 {\n" ">> +\t\t\tcompatible = \"arm,cortex-a7-gic\", \"arm,cortex-a15-gic\";\n" ">> +\t\t\treg = <0x01c81000 0x1000>,\n" ">> +\t\t\t <0x01c82000 0x1000>,\n" @@ -527,7 +537,7 @@ ">> +\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\trtc: rtc at 01f00000 {\n" + ">> +\t\trtc: rtc@01f00000 {\n" ">> +\t\t\tcompatible = \"allwinner,sun6i-a31-rtc\";\n" ">> +\t\t\treg = <0x01f00000 0x54>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -545,4 +555,4 @@ "\n" Jens -dede3b8c8080fd19629fcd3482baeab23c0a8488ddb167ccf3ef1bff04bd8965 +c0535033eb0f9667765c65cfc88efc5ba48a2df5cf828448ddd2c3b95dfccf25
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.