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From: Richard Henderson <rth@twiddle.net>
To: Alvise Rigo <a.rigo@virtualopensystems.com>, qemu-devel@nongnu.org
Cc: mttcg@greensocs.com, jani.kokkonen@huawei.com,
	tech@virtualopensystems.com, claudio.fontana@huawei.com
Subject: Re: [Qemu-devel] [RFC 4/5] tcg-op: create new TCG qemu_ldlink and qemu_stcond instructions
Date: Thu, 07 May 2015 10:58:13 -0700	[thread overview]
Message-ID: <554BA7B5.10009@twiddle.net> (raw)
In-Reply-To: <1430926687-25875-5-git-send-email-a.rigo@virtualopensystems.com>

On 05/06/2015 08:38 AM, Alvise Rigo wrote:
> +/* An output operand to return the StoreConditional result */
> +static void gen_stcond_i32(TCGOpcode opc, TCGv_i32 is_dirty, TCGv_i32 val,
> +                         TCGv addr, TCGMemOp memop, TCGArg idx)
> +{
> +    tcg_gen_op5ii_i32(opc, is_dirty, val, addr, memop, idx);
> +}

This is the wrong way to go about this.  I think you should merely add an EXCL
bit to TCGMemOp, and add no new opcodes at all.


r~

  reply	other threads:[~2015-05-07 17:58 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-06 15:38 [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation Alvise Rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 1/5] exec: Add new exclusive bitmap to ram_list Alvise Rigo
2015-05-07 17:12   ` Richard Henderson
2015-05-11  7:48     ` alvise rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 2/5] Add new TLB_EXCL flag Alvise Rigo
2015-05-07 17:25   ` Richard Henderson
2015-05-11  7:47     ` alvise rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 3/5] softmmu: Add helpers for a new slow-path Alvise Rigo
2015-05-07 17:56   ` Richard Henderson
2015-05-11  8:07     ` alvise rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 4/5] tcg-op: create new TCG qemu_ldlink and qemu_stcond instructions Alvise Rigo
2015-05-07 17:58   ` Richard Henderson [this message]
2015-05-11  8:12     ` alvise rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 5/5] target-arm: translate: implement qemu_ldlink and qemu_stcond ops Alvise Rigo
2015-05-06 15:51 ` [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation Paolo Bonzini
2015-05-06 16:00   ` Mark Burton
2015-05-06 16:21     ` alvise rigo
2015-05-06 15:55 ` Mark Burton
2015-05-06 16:19   ` alvise rigo
2015-05-06 16:20     ` Mark Burton
2015-05-08 15:22 ` Alex Bennée
2015-05-11  9:08   ` alvise rigo
2015-05-08 18:29 ` Emilio G. Cota
2015-05-11  9:10   ` alvise rigo
2015-05-26 21:51     ` Emilio G. Cota
2015-05-27  7:20       ` alvise rigo
2015-05-27  8:51         ` Alex Bennée

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