From mboxrd@z Thu Jan 1 00:00:00 1970 From: Razvan Cojocaru Subject: Re: [PATCH 1/5] xen/vm_event: Added support for XSETBV events Date: Fri, 08 May 2015 09:18:13 +0300 Message-ID: <554C5525.2030701@bitdefender.com> References: <1430932352-4289-1-git-send-email-rcojocaru@bitdefender.com> <1430932352-4289-2-git-send-email-rcojocaru@bitdefender.com> <554BA904.2020501@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <554BA904.2020501@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Andrew Cooper , xen-devel@lists.xen.org Cc: kevin.tian@intel.com, keir@xen.org, ian.campbell@citrix.com, stefano.stabellini@eu.citrix.com, ian.jackson@eu.citrix.com, eddie.dong@intel.com, tim@xen.org, jbeulich@suse.com, Aravind.Gopalakrishnan@amd.com, jun.nakajima@intel.com, wei.liu2@citrix.com, boris.ostrovsky@oracle.com, suravee.suthikulpanit@amd.com List-Id: xen-devel@lists.xenproject.org On 05/07/2015 09:03 PM, Andrew Cooper wrote: > In an effort to be architecture neutral, it might be an idea to have > something like > > struct vm_event_write_cr { > uint64_t index; > uint64_t old_val, new_val; > }; > > And have a per-arch index of control registers, such as > > X86_CR0 > X86_CR3 > X86_CR4 > X86_XCR0 > ... > ARM32_$foo > > (See also my reply to Tim on this thread) Sure, if everyone thinks this is the way forward, I can submit a patch for that as well (would you prefer it within, or outside the series?). Thanks, Razvan