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diff for duplicates of <554F1C56.20303@redhat.com>

diff --git a/a/1.txt b/N1/1.txt
index 709f1ff..9eae163 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -7,7 +7,7 @@ On 10-05-15 08:46, Vishnu Patekar wrote:
 >
 > I don't have a23 device, however, dts got compiled.
 >
-> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>
+> Signed-off-by: VishnuPatekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
 
 Please edit ~/.gitconfig and add:
 
@@ -109,7 +109,7 @@ Hans
 > -		#size-cells = <1>;
 > -		ranges;
 > -
-> -		framebuffer at 0 {
+> -		framebuffer@0 {
 > -			compatible = "allwinner,simple-framebuffer",
 > -				     "simple-framebuffer";
 > -			allwinner,pipeline = "de_be0-lcd0";
@@ -156,7 +156,7 @@ Hans
 > -			clock-output-names = "osc32k";
 > -		};
 > -
-> -		pll1: clk at 01c20000 {
+> -		pll1: clk@01c20000 {
 > -			#clock-cells = <0>;
 > -			compatible = "allwinner,sun8i-a23-pll1-clk";
 > -			reg = <0x01c20000 0x4>;
@@ -171,7 +171,7 @@ Hans
 >   			clock-output-names = "pll5";
 >   		};
 >
-> -		pll6: clk at 01c20028 {
+> -		pll6: clk@01c20028 {
 > -			#clock-cells = <1>;
 > -			compatible = "allwinner,sun6i-a31-pll6-clk";
 > -			reg = <0x01c20028 0x4>;
@@ -179,7 +179,7 @@ Hans
 > -			clock-output-names = "pll6", "pll6x2";
 > -		};
 > -
-> -		cpu: cpu_clk at 01c20050 {
+> -		cpu: cpu_clk@01c20050 {
 > -			#clock-cells = <0>;
 > -			compatible = "allwinner,sun4i-a10-cpu-clk";
 > -			reg = <0x01c20050 0x4>;
@@ -194,14 +194,14 @@ Hans
 > -			clock-output-names = "cpu";
 > -		};
 > -
->   		axi: axi_clk at 01c20050 {
+>   		axi: axi_clk@01c20050 {
 >   			#clock-cells = <0>;
 >   			compatible = "allwinner,sun8i-a23-axi-clk";
 > @@ -168,22 +85,6 @@
 >   			clock-output-names = "axi";
 >   		};
 >
-> -		ahb1: ahb1_clk at 01c20054 {
+> -		ahb1: ahb1_clk@01c20054 {
 > -			#clock-cells = <0>;
 > -			compatible = "allwinner,sun6i-a31-ahb1-clk";
 > -			reg = <0x01c20054 0x4>;
@@ -209,7 +209,7 @@ Hans
 > -			clock-output-names = "ahb1";
 > -		};
 > -
-> -		apb1: apb1_clk at 01c20054 {
+> -		apb1: apb1_clk@01c20054 {
 > -			#clock-cells = <0>;
 > -			compatible = "allwinner,sun4i-a10-apb0-clk";
 > -			reg = <0x01c20054 0x4>;
@@ -217,14 +217,14 @@ Hans
 > -			clock-output-names = "apb1";
 > -		};
 > -
->   		ahb1_gates: clk at 01c20060 {
+>   		ahb1_gates: clk@01c20060 {
 >   			#clock-cells = <1>;
 >   			compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
 > @@ -228,36 +129,6 @@
 >   					"apb2_uart3", "apb2_uart4";
 >   		};
 >
-> -		mmc0_clk: clk at 01c20088 {
+> -		mmc0_clk: clk@01c20088 {
 > -			#clock-cells = <1>;
 > -			compatible = "allwinner,sun4i-a10-mmc-clk";
 > -			reg = <0x01c20088 0x4>;
@@ -234,7 +234,7 @@ Hans
 > -					     "mmc0_sample";
 > -		};
 > -
-> -		mmc1_clk: clk at 01c2008c {
+> -		mmc1_clk: clk@01c2008c {
 > -			#clock-cells = <1>;
 > -			compatible = "allwinner,sun4i-a10-mmc-clk";
 > -			reg = <0x01c2008c 0x4>;
@@ -244,7 +244,7 @@ Hans
 > -					     "mmc1_sample";
 > -		};
 > -
-> -		mmc2_clk: clk at 01c20090 {
+> -		mmc2_clk: clk@01c20090 {
 > -			#clock-cells = <1>;
 > -			compatible = "allwinner,sun4i-a10-mmc-clk";
 > -			reg = <0x01c20090 0x4>;
@@ -254,26 +254,26 @@ Hans
 > -					     "mmc2_sample";
 > -		};
 > -
->   		mbus_clk: clk at 01c2015c {
+>   		mbus_clk: clk@01c2015c {
 >   			#clock-cells = <0>;
 >   			compatible = "allwinner,sun8i-a23-mbus-clk";
 > @@ -268,11 +139,6 @@
 >   	};
 >
->   	soc at 01c00000 {
+>   	soc@01c00000 {
 > -		compatible = "simple-bus";
 > -		#address-cells = <1>;
 > -		#size-cells = <1>;
 > -		ranges;
 > -
->   		dma: dma-controller at 01c02000 {
+>   		dma: dma-controller@01c02000 {
 >   			compatible = "allwinner,sun8i-a23-dma";
 >   			reg = <0x01c02000 0x1000>;
 > @@ -282,75 +148,12 @@
 >   			#dma-cells = <1>;
 >   		};
 >
-> -		mmc0: mmc at 01c0f000 {
+> -		mmc0: mmc@01c0f000 {
 > -			compatible = "allwinner,sun5i-a13-mmc";
 > -			reg = <0x01c0f000 0x1000>;
 > -			clocks = <&ahb1_gates 8>,
@@ -292,7 +292,7 @@ Hans
 > -			#size-cells = <0>;
 > -		};
 > -
-> -		mmc1: mmc at 01c10000 {
+> -		mmc1: mmc@01c10000 {
 > -			compatible = "allwinner,sun5i-a13-mmc";
 > -			reg = <0x01c10000 0x1000>;
 > -			clocks = <&ahb1_gates 9>,
@@ -311,7 +311,7 @@ Hans
 > -			#size-cells = <0>;
 > -		};
 > -
-> -		mmc2: mmc at 01c11000 {
+> -		mmc2: mmc@01c11000 {
 > -			compatible = "allwinner,sun5i-a13-mmc";
 > -			reg = <0x01c11000 0x1000>;
 > -			clocks = <&ahb1_gates 10>,
@@ -330,7 +330,7 @@ Hans
 > -			#size-cells = <0>;
 > -		};
 > -
->   		pio: pinctrl at 01c20800 {
+>   		pio: pinctrl@01c20800 {
 >   			compatible = "allwinner,sun8i-a23-pinctrl";
 > -			reg = <0x01c20800 0x400>;
 >   			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
@@ -344,52 +344,52 @@ Hans
 > -			#gpio-cells = <3>;
 > +
 >
->   			uart0_pins_a: uart0 at 0 {
+>   			uart0_pins_a: uart0@0 {
 >   				allwinner,pins = "PF2", "PF4";
 > @@ -359,20 +162,6 @@
 >   				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 >   			};
 >
-> -			mmc0_pins_a: mmc0 at 0 {
+> -			mmc0_pins_a: mmc0@0 {
 > -				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 > -				allwinner,function = "mmc0";
 > -				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 > -				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 > -			};
 > -
-> -			mmc1_pins_a: mmc1 at 0 {
+> -			mmc1_pins_a: mmc1@0 {
 > -				allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
 > -				allwinner,function = "mmc1";
 > -				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 > -				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 > -			};
 > -
->   			i2c0_pins_a: i2c0 at 0 {
+>   			i2c0_pins_a: i2c0@0 {
 >   				allwinner,pins = "PH2", "PH3";
 >   				allwinner,function = "i2c0";
 > @@ -395,38 +184,6 @@
 >   			};
 >   		};
 >
-> -		ahb1_rst: reset at 01c202c0 {
+> -		ahb1_rst: reset@01c202c0 {
 > -			#reset-cells = <1>;
 > -			compatible = "allwinner,sun6i-a31-clock-reset";
 > -			reg = <0x01c202c0 0xc>;
 > -		};
 > -
-> -		apb1_rst: reset at 01c202d0 {
+> -		apb1_rst: reset@01c202d0 {
 > -			#reset-cells = <1>;
 > -			compatible = "allwinner,sun6i-a31-clock-reset";
 > -			reg = <0x01c202d0 0x4>;
 > -		};
 > -
-> -		apb2_rst: reset at 01c202d8 {
+> -		apb2_rst: reset@01c202d8 {
 > -			#reset-cells = <1>;
 > -			compatible = "allwinner,sun6i-a31-clock-reset";
 > -			reg = <0x01c202d8 0x4>;
 > -		};
 > -
-> -		timer at 01c20c00 {
+> -		timer@01c20c00 {
 > -			compatible = "allwinner,sun4i-a10-timer";
 > -			reg = <0x01c20c00 0xa0>;
 > -			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
@@ -397,20 +397,20 @@ Hans
 > -			clocks = <&osc24M>;
 > -		};
 > -
-> -		wdt0: watchdog at 01c20ca0 {
+> -		wdt0: watchdog@01c20ca0 {
 > -			compatible = "allwinner,sun6i-a31-wdt";
 > -			reg = <0x01c20ca0 0x20>;
 > -			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 > -		};
 > -
->   		lradc: lradc at 01c22800 {
+>   		lradc: lradc@01c22800 {
 >   			compatible = "allwinner,sun4i-a10-lradc-keys";
 >   			reg = <0x01c22800 0x100>;
 > @@ -434,58 +191,6 @@
 >   			status = "disabled";
 >   		};
 >
-> -		uart0: serial at 01c28000 {
+> -		uart0: serial@01c28000 {
 > -			compatible = "snps,dw-apb-uart";
 > -			reg = <0x01c28000 0x400>;
 > -			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
@@ -423,7 +423,7 @@ Hans
 > -			status = "disabled";
 > -		};
 > -
-> -		uart1: serial at 01c28400 {
+> -		uart1: serial@01c28400 {
 > -			compatible = "snps,dw-apb-uart";
 > -			reg = <0x01c28400 0x400>;
 > -			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
@@ -436,7 +436,7 @@ Hans
 > -			status = "disabled";
 > -		};
 > -
-> -		uart2: serial at 01c28800 {
+> -		uart2: serial@01c28800 {
 > -			compatible = "snps,dw-apb-uart";
 > -			reg = <0x01c28800 0x400>;
 > -			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -449,7 +449,7 @@ Hans
 > -			status = "disabled";
 > -		};
 > -
-> -		uart3: serial at 01c28c00 {
+> -		uart3: serial@01c28c00 {
 > -			compatible = "snps,dw-apb-uart";
 > -			reg = <0x01c28c00 0x400>;
 > -			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
@@ -462,7 +462,7 @@ Hans
 > -			status = "disabled";
 > -		};
 > -
->   		uart4: serial at 01c29000 {
+>   		uart4: serial@01c29000 {
 >   			compatible = "snps,dw-apb-uart";
 >   			reg = <0x01c29000 0x400>;
 > @@ -498,136 +203,5 @@
@@ -470,7 +470,7 @@ Hans
 >   			status = "disabled";
 >   		};
 > -
-> -		i2c0: i2c at 01c2ac00 {
+> -		i2c0: i2c@01c2ac00 {
 > -			compatible = "allwinner,sun6i-a31-i2c";
 > -			reg = <0x01c2ac00 0x400>;
 > -			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
@@ -481,7 +481,7 @@ Hans
 > -			#size-cells = <0>;
 > -		};
 > -
-> -		i2c1: i2c at 01c2b000 {
+> -		i2c1: i2c@01c2b000 {
 > -			compatible = "allwinner,sun6i-a31-i2c";
 > -			reg = <0x01c2b000 0x400>;
 > -			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
@@ -492,7 +492,7 @@ Hans
 > -			#size-cells = <0>;
 > -		};
 > -
-> -		i2c2: i2c at 01c2b400 {
+> -		i2c2: i2c@01c2b400 {
 > -			compatible = "allwinner,sun6i-a31-i2c";
 > -			reg = <0x01c2b400 0x400>;
 > -			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
@@ -503,7 +503,7 @@ Hans
 > -			#size-cells = <0>;
 > -		};
 > -
-> -		gic: interrupt-controller at 01c81000 {
+> -		gic: interrupt-controller@01c81000 {
 > -			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 > -			reg = <0x01c81000 0x1000>,
 > -			      <0x01c82000 0x1000>,
@@ -514,14 +514,14 @@ Hans
 > -			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 > -		};
 > -
-> -		rtc: rtc at 01f00000 {
+> -		rtc: rtc@01f00000 {
 > -			compatible = "allwinner,sun6i-a31-rtc";
 > -			reg = <0x01f00000 0x54>;
 > -			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 > -				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 > -		};
 > -
-> -		prcm at 01f01400 {
+> -		prcm@01f01400 {
 > -			compatible = "allwinner,sun8i-a23-prcm";
 > -			reg = <0x01f01400 0x200>;
 > -
@@ -565,12 +565,12 @@ Hans
 > -			};
 > -		};
 > -
-> -		cpucfg at 01f01c00 {
+> -		cpucfg@01f01c00 {
 > -			compatible = "allwinner,sun8i-a23-cpuconfig";
 > -			reg = <0x01f01c00 0x300>;
 > -		};
 > -
-> -		r_uart: serial at 01f02800 {
+> -		r_uart: serial@01f02800 {
 > -			compatible = "snps,dw-apb-uart";
 > -			reg = <0x01f02800 0x400>;
 > -			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
@@ -581,7 +581,7 @@ Hans
 > -			status = "disabled";
 > -		};
 > -
-> -		r_pio: pinctrl at 01f02c00 {
+> -		r_pio: pinctrl@01f02c00 {
 > -			compatible = "allwinner,sun8i-a23-r-pinctrl";
 > -			reg = <0x01f02c00 0x400>;
 > -			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
@@ -593,7 +593,7 @@ Hans
 > -			#size-cells = <0>;
 > -			#gpio-cells = <3>;
 > -
-> -			r_uart_pins_a: r_uart at 0 {
+> -			r_uart_pins_a: r_uart@0 {
 > -				allwinner,pins = "PL2", "PL3";
 > -				allwinner,function = "s_uart";
 > -				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
@@ -611,7 +611,7 @@ Hans
 > +/*
 > + * Copyright 2014 Chen-Yu Tsai
 > + *
-> + * Chen-Yu Tsai <wens@csie.org>
+> + * Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
 > + *
 > + * This file is dual-licensed: you can use it either under the terms
 > + * of the GPL or the X11 license, at your option. Note that this dual
@@ -667,7 +667,7 @@ Hans
 > +		#size-cells = <1>;
 > +		ranges;
 > +
-> +		framebuffer at 0 {
+> +		framebuffer@0 {
 > +			compatible = "allwinner,simple-framebuffer",
 > +				     "simple-framebuffer";
 > +			allwinner,pipeline = "de_be0-lcd0";
@@ -705,7 +705,7 @@ Hans
 > +			clock-output-names = "osc32k";
 > +		};
 > +
-> +		pll1: clk at 01c20000 {
+> +		pll1: clk@01c20000 {
 > +			#clock-cells = <0>;
 > +			compatible = "allwinner,sun8i-a23-pll1-clk";
 > +			reg = <0x01c20000 0x4>;
@@ -713,7 +713,7 @@ Hans
 > +			clock-output-names = "pll1";
 > +		};
 > +
-> +		pll6: clk at 01c20028 {
+> +		pll6: clk@01c20028 {
 > +			#clock-cells = <1>;
 > +			compatible = "allwinner,sun6i-a31-pll6-clk";
 > +			reg = <0x01c20028 0x4>;
@@ -721,7 +721,7 @@ Hans
 > +			clock-output-names = "pll6", "pll6x2";
 > +		};
 > +
-> +		cpu: cpu_clk at 01c20050 {
+> +		cpu: cpu_clk@01c20050 {
 > +			#clock-cells = <0>;
 > +			compatible = "allwinner,sun4i-a10-cpu-clk";
 > +			reg = <0x01c20050 0x4>;
@@ -737,7 +737,7 @@ Hans
 > +		};
 > +
 > +
-> +		ahb1: ahb1_clk at 01c20054 {
+> +		ahb1: ahb1_clk@01c20054 {
 > +			#clock-cells = <0>;
 > +			compatible = "allwinner,sun6i-a31-ahb1-clk";
 > +			reg = <0x01c20054 0x4>;
@@ -745,7 +745,7 @@ Hans
 > +			clock-output-names = "ahb1";
 > +		};
 > +
-> +		apb1: apb1_clk at 01c20054 {
+> +		apb1: apb1_clk@01c20054 {
 > +			#clock-cells = <0>;
 > +			compatible = "allwinner,sun4i-a10-apb0-clk";
 > +			reg = <0x01c20054 0x4>;
@@ -753,7 +753,7 @@ Hans
 > +			clock-output-names = "apb1";
 > +		};
 > +
-> +		mmc0_clk: clk at 01c20088 {
+> +		mmc0_clk: clk@01c20088 {
 > +			#clock-cells = <1>;
 > +			compatible = "allwinner,sun4i-a10-mmc-clk";
 > +			reg = <0x01c20088 0x4>;
@@ -763,7 +763,7 @@ Hans
 > +					     "mmc0_sample";
 > +		};
 > +
-> +		mmc1_clk: clk at 01c2008c {
+> +		mmc1_clk: clk@01c2008c {
 > +			#clock-cells = <1>;
 > +			compatible = "allwinner,sun4i-a10-mmc-clk";
 > +			reg = <0x01c2008c 0x4>;
@@ -773,7 +773,7 @@ Hans
 > +					     "mmc1_sample";
 > +		};
 > +
-> +		mmc2_clk: clk at 01c20090 {
+> +		mmc2_clk: clk@01c20090 {
 > +			#clock-cells = <1>;
 > +			compatible = "allwinner,sun4i-a10-mmc-clk";
 > +			reg = <0x01c20090 0x4>;
@@ -785,14 +785,14 @@ Hans
 > +
 > +	};
 > +
-> +	soc at 01c00000 {
+> +	soc@01c00000 {
 > +		compatible = "simple-bus";
 > +		#address-cells = <1>;
 > +		#size-cells = <1>;
 > +		ranges;
 > +
 > +
-> +		mmc0: mmc at 01c0f000 {
+> +		mmc0: mmc@01c0f000 {
 > +			compatible = "allwinner,sun5i-a13-mmc";
 > +			reg = <0x01c0f000 0x1000>;
 > +			clocks = <&ahb1_gates 8>,
@@ -811,7 +811,7 @@ Hans
 > +			#size-cells = <0>;
 > +		};
 > +
-> +		mmc1: mmc at 01c10000 {
+> +		mmc1: mmc@01c10000 {
 > +			compatible = "allwinner,sun5i-a13-mmc";
 > +			reg = <0x01c10000 0x1000>;
 > +			clocks = <&ahb1_gates 9>,
@@ -830,7 +830,7 @@ Hans
 > +			#size-cells = <0>;
 > +		};
 > +
-> +		mmc2: mmc at 01c11000 {
+> +		mmc2: mmc@01c11000 {
 > +			compatible = "allwinner,sun5i-a13-mmc";
 > +			reg = <0x01c11000 0x1000>;
 > +			clocks = <&ahb1_gates 10>,
@@ -849,7 +849,7 @@ Hans
 > +			#size-cells = <0>;
 > +		};
 > +
-> +		pio: pinctrl at 01c20800 {
+> +		pio: pinctrl@01c20800 {
 > +			reg = <0x01c20800 0x400>;
 > +			clocks = <&apb1_gates 5>;
 > +			gpio-controller;
@@ -858,14 +858,14 @@ Hans
 > +			#size-cells = <0>;
 > +			#gpio-cells = <3>;
 > +
-> +			mmc0_pins_a: mmc0 at 0 {
+> +			mmc0_pins_a: mmc0@0 {
 > +				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 > +				allwinner,function = "mmc0";
 > +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 > +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 > +			};
 > +
-> +			mmc1_pins_a: mmc1 at 0 {
+> +			mmc1_pins_a: mmc1@0 {
 > +				allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
 > +				allwinner,function = "mmc1";
 > +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
@@ -873,25 +873,25 @@ Hans
 > +			};
 > +		};
 > +
-> +		ahb1_rst: reset at 01c202c0 {
+> +		ahb1_rst: reset@01c202c0 {
 > +			#reset-cells = <1>;
 > +			compatible = "allwinner,sun6i-a31-clock-reset";
 > +			reg = <0x01c202c0 0xc>;
 > +		};
 > +
-> +		apb1_rst: reset at 01c202d0 {
+> +		apb1_rst: reset@01c202d0 {
 > +			#reset-cells = <1>;
 > +			compatible = "allwinner,sun6i-a31-clock-reset";
 > +			reg = <0x01c202d0 0x4>;
 > +		};
 > +
-> +		apb2_rst: reset at 01c202d8 {
+> +		apb2_rst: reset@01c202d8 {
 > +			#reset-cells = <1>;
 > +			compatible = "allwinner,sun6i-a31-clock-reset";
 > +			reg = <0x01c202d8 0x4>;
 > +		};
 > +
-> +		timer at 01c20c00 {
+> +		timer@01c20c00 {
 > +			compatible = "allwinner,sun4i-a10-timer";
 > +			reg = <0x01c20c00 0xa0>;
 > +			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
@@ -899,13 +899,13 @@ Hans
 > +			clocks = <&osc24M>;
 > +		};
 > +
-> +		wdt0: watchdog at 01c20ca0 {
+> +		wdt0: watchdog@01c20ca0 {
 > +			compatible = "allwinner,sun6i-a31-wdt";
 > +			reg = <0x01c20ca0 0x20>;
 > +			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 > +		};
 > +
-> +		uart0: serial at 01c28000 {
+> +		uart0: serial@01c28000 {
 > +			compatible = "snps,dw-apb-uart";
 > +			reg = <0x01c28000 0x400>;
 > +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
@@ -918,7 +918,7 @@ Hans
 > +			status = "disabled";
 > +		};
 > +
-> +		uart1: serial at 01c28400 {
+> +		uart1: serial@01c28400 {
 > +			compatible = "snps,dw-apb-uart";
 > +			reg = <0x01c28400 0x400>;
 > +			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
@@ -931,7 +931,7 @@ Hans
 > +			status = "disabled";
 > +		};
 > +
-> +		uart2: serial at 01c28800 {
+> +		uart2: serial@01c28800 {
 > +			compatible = "snps,dw-apb-uart";
 > +			reg = <0x01c28800 0x400>;
 > +			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -944,7 +944,7 @@ Hans
 > +			status = "disabled";
 > +		};
 > +
-> +		uart3: serial at 01c28c00 {
+> +		uart3: serial@01c28c00 {
 > +			compatible = "snps,dw-apb-uart";
 > +			reg = <0x01c28c00 0x400>;
 > +			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
@@ -957,7 +957,7 @@ Hans
 > +			status = "disabled";
 > +		};
 > +
-> +		i2c0: i2c at 01c2ac00 {
+> +		i2c0: i2c@01c2ac00 {
 > +			compatible = "allwinner,sun6i-a31-i2c";
 > +			reg = <0x01c2ac00 0x400>;
 > +			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
@@ -968,7 +968,7 @@ Hans
 > +			#size-cells = <0>;
 > +		};
 > +
-> +		i2c1: i2c at 01c2b000 {
+> +		i2c1: i2c@01c2b000 {
 > +			compatible = "allwinner,sun6i-a31-i2c";
 > +			reg = <0x01c2b000 0x400>;
 > +			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
@@ -979,7 +979,7 @@ Hans
 > +			#size-cells = <0>;
 > +		};
 > +
-> +		i2c2: i2c at 01c2b400 {
+> +		i2c2: i2c@01c2b400 {
 > +			compatible = "allwinner,sun6i-a31-i2c";
 > +			reg = <0x01c2b400 0x400>;
 > +			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
@@ -990,7 +990,7 @@ Hans
 > +			#size-cells = <0>;
 > +		};
 > +
-> +		gic: interrupt-controller at 01c81000 {
+> +		gic: interrupt-controller@01c81000 {
 > +			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 > +			reg = <0x01c81000 0x1000>,
 > +			      <0x01c82000 0x1000>,
@@ -1001,14 +1001,14 @@ Hans
 > +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 > +		};
 > +
-> +		rtc: rtc at 01f00000 {
+> +		rtc: rtc@01f00000 {
 > +			compatible = "allwinner,sun6i-a31-rtc";
 > +			reg = <0x01f00000 0x54>;
 > +			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 > +				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 > +		};
 > +
-> +		prcm at 01f01400 {
+> +		prcm@01f01400 {
 > +			compatible = "allwinner,sun8i-a23-prcm";
 > +			reg = <0x01f01400 0x200>;
 > +
@@ -1052,12 +1052,12 @@ Hans
 > +			};
 > +		};
 > +
-> +		cpucfg at 01f01c00 {
+> +		cpucfg@01f01c00 {
 > +			compatible = "allwinner,sun8i-a23-cpuconfig";
 > +			reg = <0x01f01c00 0x300>;
 > +		};
 > +
-> +		r_uart: serial at 01f02800 {
+> +		r_uart: serial@01f02800 {
 > +			compatible = "snps,dw-apb-uart";
 > +			reg = <0x01f02800 0x400>;
 > +			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
@@ -1068,7 +1068,7 @@ Hans
 > +			status = "disabled";
 > +		};
 > +
-> +		r_pio: pinctrl at 01f02c00 {
+> +		r_pio: pinctrl@01f02c00 {
 > +			compatible = "allwinner,sun8i-a23-r-pinctrl";
 > +			reg = <0x01f02c00 0x400>;
 > +			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
@@ -1080,7 +1080,7 @@ Hans
 > +			#size-cells = <0>;
 > +			#gpio-cells = <3>;
 > +
-> +			r_uart_pins_a: r_uart at 0 {
+> +			r_uart_pins_a: r_uart@0 {
 > +				allwinner,pins = "PL2", "PL3";
 > +				allwinner,function = "s_uart";
 > +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
diff --git a/a/content_digest b/N1/content_digest
index 1e3e94e..14736b9 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,9 +1,21 @@
  "ref\01431240383-12763-1-git-send-email-vishnupatekar0510@gmail.com\0"
  "ref\01431240383-12763-5-git-send-email-vishnupatekar0510@gmail.com\0"
- "From\0hdegoede@redhat.com (Hans de Goede)\0"
- "Subject\0[PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi\0"
+ "ref\01431240383-12763-5-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0"
+ "From\0Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>\0"
+ "Subject\0Re: [PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi\0"
  "Date\0Sun, 10 May 2015 10:52:38 +0200\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
+ "To\0Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>"
+  maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org
+  emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org
+  linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org
+ " robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org\0"
+ "Cc\0wens-jdAy2FN1RRM@public.gmane.org"
+  jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
+  arnd-r2nGTMty4D4@public.gmane.org
+  linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
+  linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
+  linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
+ " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0"
  "\00:1\0"
  "b\0"
  "Hi,\n"
@@ -15,7 +27,7 @@
  ">\n"
  "> I don't have a23 device, however, dts got compiled.\n"
  ">\n"
- "> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>\n"
+ "> Signed-off-by: VishnuPatekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n"
  "\n"
  "Please edit ~/.gitconfig and add:\n"
  "\n"
@@ -117,7 +129,7 @@
  "> -\t\t#size-cells = <1>;\n"
  "> -\t\tranges;\n"
  "> -\n"
- "> -\t\tframebuffer at 0 {\n"
+ "> -\t\tframebuffer@0 {\n"
  "> -\t\t\tcompatible = \"allwinner,simple-framebuffer\",\n"
  "> -\t\t\t\t     \"simple-framebuffer\";\n"
  "> -\t\t\tallwinner,pipeline = \"de_be0-lcd0\";\n"
@@ -164,7 +176,7 @@
  "> -\t\t\tclock-output-names = \"osc32k\";\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tpll1: clk at 01c20000 {\n"
+ "> -\t\tpll1: clk@01c20000 {\n"
  "> -\t\t\t#clock-cells = <0>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n"
  "> -\t\t\treg = <0x01c20000 0x4>;\n"
@@ -179,7 +191,7 @@
  ">   \t\t\tclock-output-names = \"pll5\";\n"
  ">   \t\t};\n"
  ">\n"
- "> -\t\tpll6: clk at 01c20028 {\n"
+ "> -\t\tpll6: clk@01c20028 {\n"
  "> -\t\t\t#clock-cells = <1>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n"
  "> -\t\t\treg = <0x01c20028 0x4>;\n"
@@ -187,7 +199,7 @@
  "> -\t\t\tclock-output-names = \"pll6\", \"pll6x2\";\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tcpu: cpu_clk at 01c20050 {\n"
+ "> -\t\tcpu: cpu_clk@01c20050 {\n"
  "> -\t\t\t#clock-cells = <0>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n"
  "> -\t\t\treg = <0x01c20050 0x4>;\n"
@@ -202,14 +214,14 @@
  "> -\t\t\tclock-output-names = \"cpu\";\n"
  "> -\t\t};\n"
  "> -\n"
- ">   \t\taxi: axi_clk at 01c20050 {\n"
+ ">   \t\taxi: axi_clk@01c20050 {\n"
  ">   \t\t\t#clock-cells = <0>;\n"
  ">   \t\t\tcompatible = \"allwinner,sun8i-a23-axi-clk\";\n"
  "> @@ -168,22 +85,6 @@\n"
  ">   \t\t\tclock-output-names = \"axi\";\n"
  ">   \t\t};\n"
  ">\n"
- "> -\t\tahb1: ahb1_clk at 01c20054 {\n"
+ "> -\t\tahb1: ahb1_clk@01c20054 {\n"
  "> -\t\t\t#clock-cells = <0>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n"
  "> -\t\t\treg = <0x01c20054 0x4>;\n"
@@ -217,7 +229,7 @@
  "> -\t\t\tclock-output-names = \"ahb1\";\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tapb1: apb1_clk at 01c20054 {\n"
+ "> -\t\tapb1: apb1_clk@01c20054 {\n"
  "> -\t\t\t#clock-cells = <0>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n"
  "> -\t\t\treg = <0x01c20054 0x4>;\n"
@@ -225,14 +237,14 @@
  "> -\t\t\tclock-output-names = \"apb1\";\n"
  "> -\t\t};\n"
  "> -\n"
- ">   \t\tahb1_gates: clk at 01c20060 {\n"
+ ">   \t\tahb1_gates: clk@01c20060 {\n"
  ">   \t\t\t#clock-cells = <1>;\n"
  ">   \t\t\tcompatible = \"allwinner,sun8i-a23-ahb1-gates-clk\";\n"
  "> @@ -228,36 +129,6 @@\n"
  ">   \t\t\t\t\t\"apb2_uart3\", \"apb2_uart4\";\n"
  ">   \t\t};\n"
  ">\n"
- "> -\t\tmmc0_clk: clk at 01c20088 {\n"
+ "> -\t\tmmc0_clk: clk@01c20088 {\n"
  "> -\t\t\t#clock-cells = <1>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n"
  "> -\t\t\treg = <0x01c20088 0x4>;\n"
@@ -242,7 +254,7 @@
  "> -\t\t\t\t\t     \"mmc0_sample\";\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tmmc1_clk: clk at 01c2008c {\n"
+ "> -\t\tmmc1_clk: clk@01c2008c {\n"
  "> -\t\t\t#clock-cells = <1>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n"
  "> -\t\t\treg = <0x01c2008c 0x4>;\n"
@@ -252,7 +264,7 @@
  "> -\t\t\t\t\t     \"mmc1_sample\";\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tmmc2_clk: clk at 01c20090 {\n"
+ "> -\t\tmmc2_clk: clk@01c20090 {\n"
  "> -\t\t\t#clock-cells = <1>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n"
  "> -\t\t\treg = <0x01c20090 0x4>;\n"
@@ -262,26 +274,26 @@
  "> -\t\t\t\t\t     \"mmc2_sample\";\n"
  "> -\t\t};\n"
  "> -\n"
- ">   \t\tmbus_clk: clk at 01c2015c {\n"
+ ">   \t\tmbus_clk: clk@01c2015c {\n"
  ">   \t\t\t#clock-cells = <0>;\n"
  ">   \t\t\tcompatible = \"allwinner,sun8i-a23-mbus-clk\";\n"
  "> @@ -268,11 +139,6 @@\n"
  ">   \t};\n"
  ">\n"
- ">   \tsoc at 01c00000 {\n"
+ ">   \tsoc@01c00000 {\n"
  "> -\t\tcompatible = \"simple-bus\";\n"
  "> -\t\t#address-cells = <1>;\n"
  "> -\t\t#size-cells = <1>;\n"
  "> -\t\tranges;\n"
  "> -\n"
- ">   \t\tdma: dma-controller at 01c02000 {\n"
+ ">   \t\tdma: dma-controller@01c02000 {\n"
  ">   \t\t\tcompatible = \"allwinner,sun8i-a23-dma\";\n"
  ">   \t\t\treg = <0x01c02000 0x1000>;\n"
  "> @@ -282,75 +148,12 @@\n"
  ">   \t\t\t#dma-cells = <1>;\n"
  ">   \t\t};\n"
  ">\n"
- "> -\t\tmmc0: mmc at 01c0f000 {\n"
+ "> -\t\tmmc0: mmc@01c0f000 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n"
  "> -\t\t\treg = <0x01c0f000 0x1000>;\n"
  "> -\t\t\tclocks = <&ahb1_gates 8>,\n"
@@ -300,7 +312,7 @@
  "> -\t\t\t#size-cells = <0>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tmmc1: mmc at 01c10000 {\n"
+ "> -\t\tmmc1: mmc@01c10000 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n"
  "> -\t\t\treg = <0x01c10000 0x1000>;\n"
  "> -\t\t\tclocks = <&ahb1_gates 9>,\n"
@@ -319,7 +331,7 @@
  "> -\t\t\t#size-cells = <0>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tmmc2: mmc at 01c11000 {\n"
+ "> -\t\tmmc2: mmc@01c11000 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n"
  "> -\t\t\treg = <0x01c11000 0x1000>;\n"
  "> -\t\t\tclocks = <&ahb1_gates 10>,\n"
@@ -338,7 +350,7 @@
  "> -\t\t\t#size-cells = <0>;\n"
  "> -\t\t};\n"
  "> -\n"
- ">   \t\tpio: pinctrl at 01c20800 {\n"
+ ">   \t\tpio: pinctrl@01c20800 {\n"
  ">   \t\t\tcompatible = \"allwinner,sun8i-a23-pinctrl\";\n"
  "> -\t\t\treg = <0x01c20800 0x400>;\n"
  ">   \t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n"
@@ -352,52 +364,52 @@
  "> -\t\t\t#gpio-cells = <3>;\n"
  "> +\n"
  ">\n"
- ">   \t\t\tuart0_pins_a: uart0 at 0 {\n"
+ ">   \t\t\tuart0_pins_a: uart0@0 {\n"
  ">   \t\t\t\tallwinner,pins = \"PF2\", \"PF4\";\n"
  "> @@ -359,20 +162,6 @@\n"
  ">   \t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n"
  ">   \t\t\t};\n"
  ">\n"
- "> -\t\t\tmmc0_pins_a: mmc0 at 0 {\n"
+ "> -\t\t\tmmc0_pins_a: mmc0@0 {\n"
  "> -\t\t\t\tallwinner,pins = \"PF0\",\"PF1\",\"PF2\",\"PF3\",\"PF4\",\"PF5\";\n"
  "> -\t\t\t\tallwinner,function = \"mmc0\";\n"
  "> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n"
  "> -\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n"
  "> -\t\t\t};\n"
  "> -\n"
- "> -\t\t\tmmc1_pins_a: mmc1 at 0 {\n"
+ "> -\t\t\tmmc1_pins_a: mmc1@0 {\n"
  "> -\t\t\t\tallwinner,pins = \"PG0\",\"PG1\",\"PG2\",\"PG3\",\"PG4\",\"PG5\";\n"
  "> -\t\t\t\tallwinner,function = \"mmc1\";\n"
  "> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n"
  "> -\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n"
  "> -\t\t\t};\n"
  "> -\n"
- ">   \t\t\ti2c0_pins_a: i2c0 at 0 {\n"
+ ">   \t\t\ti2c0_pins_a: i2c0@0 {\n"
  ">   \t\t\t\tallwinner,pins = \"PH2\", \"PH3\";\n"
  ">   \t\t\t\tallwinner,function = \"i2c0\";\n"
  "> @@ -395,38 +184,6 @@\n"
  ">   \t\t\t};\n"
  ">   \t\t};\n"
  ">\n"
- "> -\t\tahb1_rst: reset at 01c202c0 {\n"
+ "> -\t\tahb1_rst: reset@01c202c0 {\n"
  "> -\t\t\t#reset-cells = <1>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n"
  "> -\t\t\treg = <0x01c202c0 0xc>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tapb1_rst: reset at 01c202d0 {\n"
+ "> -\t\tapb1_rst: reset@01c202d0 {\n"
  "> -\t\t\t#reset-cells = <1>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n"
  "> -\t\t\treg = <0x01c202d0 0x4>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tapb2_rst: reset at 01c202d8 {\n"
+ "> -\t\tapb2_rst: reset@01c202d8 {\n"
  "> -\t\t\t#reset-cells = <1>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n"
  "> -\t\t\treg = <0x01c202d8 0x4>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\ttimer at 01c20c00 {\n"
+ "> -\t\ttimer@01c20c00 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun4i-a10-timer\";\n"
  "> -\t\t\treg = <0x01c20c00 0xa0>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,\n"
@@ -405,20 +417,20 @@
  "> -\t\t\tclocks = <&osc24M>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\twdt0: watchdog at 01c20ca0 {\n"
+ "> -\t\twdt0: watchdog@01c20ca0 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-wdt\";\n"
  "> -\t\t\treg = <0x01c20ca0 0x20>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;\n"
  "> -\t\t};\n"
  "> -\n"
- ">   \t\tlradc: lradc at 01c22800 {\n"
+ ">   \t\tlradc: lradc@01c22800 {\n"
  ">   \t\t\tcompatible = \"allwinner,sun4i-a10-lradc-keys\";\n"
  ">   \t\t\treg = <0x01c22800 0x100>;\n"
  "> @@ -434,58 +191,6 @@\n"
  ">   \t\t\tstatus = \"disabled\";\n"
  ">   \t\t};\n"
  ">\n"
- "> -\t\tuart0: serial at 01c28000 {\n"
+ "> -\t\tuart0: serial@01c28000 {\n"
  "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> -\t\t\treg = <0x01c28000 0x400>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -431,7 +443,7 @@
  "> -\t\t\tstatus = \"disabled\";\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tuart1: serial at 01c28400 {\n"
+ "> -\t\tuart1: serial@01c28400 {\n"
  "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> -\t\t\treg = <0x01c28400 0x400>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -444,7 +456,7 @@
  "> -\t\t\tstatus = \"disabled\";\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tuart2: serial at 01c28800 {\n"
+ "> -\t\tuart2: serial@01c28800 {\n"
  "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> -\t\t\treg = <0x01c28800 0x400>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -457,7 +469,7 @@
  "> -\t\t\tstatus = \"disabled\";\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tuart3: serial at 01c28c00 {\n"
+ "> -\t\tuart3: serial@01c28c00 {\n"
  "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> -\t\t\treg = <0x01c28c00 0x400>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -470,7 +482,7 @@
  "> -\t\t\tstatus = \"disabled\";\n"
  "> -\t\t};\n"
  "> -\n"
- ">   \t\tuart4: serial at 01c29000 {\n"
+ ">   \t\tuart4: serial@01c29000 {\n"
  ">   \t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  ">   \t\t\treg = <0x01c29000 0x400>;\n"
  "> @@ -498,136 +203,5 @@\n"
@@ -478,7 +490,7 @@
  ">   \t\t\tstatus = \"disabled\";\n"
  ">   \t\t};\n"
  "> -\n"
- "> -\t\ti2c0: i2c at 01c2ac00 {\n"
+ "> -\t\ti2c0: i2c@01c2ac00 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n"
  "> -\t\t\treg = <0x01c2ac00 0x400>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -489,7 +501,7 @@
  "> -\t\t\t#size-cells = <0>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\ti2c1: i2c at 01c2b000 {\n"
+ "> -\t\ti2c1: i2c@01c2b000 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n"
  "> -\t\t\treg = <0x01c2b000 0x400>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -500,7 +512,7 @@
  "> -\t\t\t#size-cells = <0>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\ti2c2: i2c at 01c2b400 {\n"
+ "> -\t\ti2c2: i2c@01c2b400 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n"
  "> -\t\t\treg = <0x01c2b400 0x400>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -511,7 +523,7 @@
  "> -\t\t\t#size-cells = <0>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tgic: interrupt-controller at 01c81000 {\n"
+ "> -\t\tgic: interrupt-controller@01c81000 {\n"
  "> -\t\t\tcompatible = \"arm,cortex-a7-gic\", \"arm,cortex-a15-gic\";\n"
  "> -\t\t\treg = <0x01c81000 0x1000>,\n"
  "> -\t\t\t      <0x01c82000 0x1000>,\n"
@@ -522,14 +534,14 @@
  "> -\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\trtc: rtc at 01f00000 {\n"
+ "> -\t\trtc: rtc@01f00000 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-rtc\";\n"
  "> -\t\t\treg = <0x01f00000 0x54>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,\n"
  "> -\t\t\t\t     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tprcm at 01f01400 {\n"
+ "> -\t\tprcm@01f01400 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun8i-a23-prcm\";\n"
  "> -\t\t\treg = <0x01f01400 0x200>;\n"
  "> -\n"
@@ -573,12 +585,12 @@
  "> -\t\t\t};\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tcpucfg at 01f01c00 {\n"
+ "> -\t\tcpucfg@01f01c00 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun8i-a23-cpuconfig\";\n"
  "> -\t\t\treg = <0x01f01c00 0x300>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tr_uart: serial at 01f02800 {\n"
+ "> -\t\tr_uart: serial@01f02800 {\n"
  "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> -\t\t\treg = <0x01f02800 0x400>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -589,7 +601,7 @@
  "> -\t\t\tstatus = \"disabled\";\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tr_pio: pinctrl at 01f02c00 {\n"
+ "> -\t\tr_pio: pinctrl@01f02c00 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun8i-a23-r-pinctrl\";\n"
  "> -\t\t\treg = <0x01f02c00 0x400>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -601,7 +613,7 @@
  "> -\t\t\t#size-cells = <0>;\n"
  "> -\t\t\t#gpio-cells = <3>;\n"
  "> -\n"
- "> -\t\t\tr_uart_pins_a: r_uart at 0 {\n"
+ "> -\t\t\tr_uart_pins_a: r_uart@0 {\n"
  "> -\t\t\t\tallwinner,pins = \"PL2\", \"PL3\";\n"
  "> -\t\t\t\tallwinner,function = \"s_uart\";\n"
  "> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n"
@@ -619,7 +631,7 @@
  "> +/*\n"
  "> + * Copyright 2014 Chen-Yu Tsai\n"
  "> + *\n"
- "> + * Chen-Yu Tsai <wens@csie.org>\n"
+ "> + * Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>\n"
  "> + *\n"
  "> + * This file is dual-licensed: you can use it either under the terms\n"
  "> + * of the GPL or the X11 license, at your option. Note that this dual\n"
@@ -675,7 +687,7 @@
  "> +\t\t#size-cells = <1>;\n"
  "> +\t\tranges;\n"
  "> +\n"
- "> +\t\tframebuffer at 0 {\n"
+ "> +\t\tframebuffer@0 {\n"
  "> +\t\t\tcompatible = \"allwinner,simple-framebuffer\",\n"
  "> +\t\t\t\t     \"simple-framebuffer\";\n"
  "> +\t\t\tallwinner,pipeline = \"de_be0-lcd0\";\n"
@@ -713,7 +725,7 @@
  "> +\t\t\tclock-output-names = \"osc32k\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tpll1: clk at 01c20000 {\n"
+ "> +\t\tpll1: clk@01c20000 {\n"
  "> +\t\t\t#clock-cells = <0>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n"
  "> +\t\t\treg = <0x01c20000 0x4>;\n"
@@ -721,7 +733,7 @@
  "> +\t\t\tclock-output-names = \"pll1\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tpll6: clk at 01c20028 {\n"
+ "> +\t\tpll6: clk@01c20028 {\n"
  "> +\t\t\t#clock-cells = <1>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n"
  "> +\t\t\treg = <0x01c20028 0x4>;\n"
@@ -729,7 +741,7 @@
  "> +\t\t\tclock-output-names = \"pll6\", \"pll6x2\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tcpu: cpu_clk at 01c20050 {\n"
+ "> +\t\tcpu: cpu_clk@01c20050 {\n"
  "> +\t\t\t#clock-cells = <0>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n"
  "> +\t\t\treg = <0x01c20050 0x4>;\n"
@@ -745,7 +757,7 @@
  "> +\t\t};\n"
  "> +\n"
  "> +\n"
- "> +\t\tahb1: ahb1_clk at 01c20054 {\n"
+ "> +\t\tahb1: ahb1_clk@01c20054 {\n"
  "> +\t\t\t#clock-cells = <0>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n"
  "> +\t\t\treg = <0x01c20054 0x4>;\n"
@@ -753,7 +765,7 @@
  "> +\t\t\tclock-output-names = \"ahb1\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tapb1: apb1_clk at 01c20054 {\n"
+ "> +\t\tapb1: apb1_clk@01c20054 {\n"
  "> +\t\t\t#clock-cells = <0>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n"
  "> +\t\t\treg = <0x01c20054 0x4>;\n"
@@ -761,7 +773,7 @@
  "> +\t\t\tclock-output-names = \"apb1\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tmmc0_clk: clk at 01c20088 {\n"
+ "> +\t\tmmc0_clk: clk@01c20088 {\n"
  "> +\t\t\t#clock-cells = <1>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n"
  "> +\t\t\treg = <0x01c20088 0x4>;\n"
@@ -771,7 +783,7 @@
  "> +\t\t\t\t\t     \"mmc0_sample\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tmmc1_clk: clk at 01c2008c {\n"
+ "> +\t\tmmc1_clk: clk@01c2008c {\n"
  "> +\t\t\t#clock-cells = <1>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n"
  "> +\t\t\treg = <0x01c2008c 0x4>;\n"
@@ -781,7 +793,7 @@
  "> +\t\t\t\t\t     \"mmc1_sample\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tmmc2_clk: clk at 01c20090 {\n"
+ "> +\t\tmmc2_clk: clk@01c20090 {\n"
  "> +\t\t\t#clock-cells = <1>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n"
  "> +\t\t\treg = <0x01c20090 0x4>;\n"
@@ -793,14 +805,14 @@
  "> +\n"
  "> +\t};\n"
  "> +\n"
- "> +\tsoc at 01c00000 {\n"
+ "> +\tsoc@01c00000 {\n"
  "> +\t\tcompatible = \"simple-bus\";\n"
  "> +\t\t#address-cells = <1>;\n"
  "> +\t\t#size-cells = <1>;\n"
  "> +\t\tranges;\n"
  "> +\n"
  "> +\n"
- "> +\t\tmmc0: mmc at 01c0f000 {\n"
+ "> +\t\tmmc0: mmc@01c0f000 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n"
  "> +\t\t\treg = <0x01c0f000 0x1000>;\n"
  "> +\t\t\tclocks = <&ahb1_gates 8>,\n"
@@ -819,7 +831,7 @@
  "> +\t\t\t#size-cells = <0>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tmmc1: mmc at 01c10000 {\n"
+ "> +\t\tmmc1: mmc@01c10000 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n"
  "> +\t\t\treg = <0x01c10000 0x1000>;\n"
  "> +\t\t\tclocks = <&ahb1_gates 9>,\n"
@@ -838,7 +850,7 @@
  "> +\t\t\t#size-cells = <0>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tmmc2: mmc at 01c11000 {\n"
+ "> +\t\tmmc2: mmc@01c11000 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n"
  "> +\t\t\treg = <0x01c11000 0x1000>;\n"
  "> +\t\t\tclocks = <&ahb1_gates 10>,\n"
@@ -857,7 +869,7 @@
  "> +\t\t\t#size-cells = <0>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tpio: pinctrl at 01c20800 {\n"
+ "> +\t\tpio: pinctrl@01c20800 {\n"
  "> +\t\t\treg = <0x01c20800 0x400>;\n"
  "> +\t\t\tclocks = <&apb1_gates 5>;\n"
  "> +\t\t\tgpio-controller;\n"
@@ -866,14 +878,14 @@
  "> +\t\t\t#size-cells = <0>;\n"
  "> +\t\t\t#gpio-cells = <3>;\n"
  "> +\n"
- "> +\t\t\tmmc0_pins_a: mmc0 at 0 {\n"
+ "> +\t\t\tmmc0_pins_a: mmc0@0 {\n"
  "> +\t\t\t\tallwinner,pins = \"PF0\",\"PF1\",\"PF2\",\"PF3\",\"PF4\",\"PF5\";\n"
  "> +\t\t\t\tallwinner,function = \"mmc0\";\n"
  "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n"
  "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tmmc1_pins_a: mmc1 at 0 {\n"
+ "> +\t\t\tmmc1_pins_a: mmc1@0 {\n"
  "> +\t\t\t\tallwinner,pins = \"PG0\",\"PG1\",\"PG2\",\"PG3\",\"PG4\",\"PG5\";\n"
  "> +\t\t\t\tallwinner,function = \"mmc1\";\n"
  "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n"
@@ -881,25 +893,25 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tahb1_rst: reset at 01c202c0 {\n"
+ "> +\t\tahb1_rst: reset@01c202c0 {\n"
  "> +\t\t\t#reset-cells = <1>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n"
  "> +\t\t\treg = <0x01c202c0 0xc>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tapb1_rst: reset at 01c202d0 {\n"
+ "> +\t\tapb1_rst: reset@01c202d0 {\n"
  "> +\t\t\t#reset-cells = <1>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n"
  "> +\t\t\treg = <0x01c202d0 0x4>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tapb2_rst: reset at 01c202d8 {\n"
+ "> +\t\tapb2_rst: reset@01c202d8 {\n"
  "> +\t\t\t#reset-cells = <1>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n"
  "> +\t\t\treg = <0x01c202d8 0x4>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\ttimer at 01c20c00 {\n"
+ "> +\t\ttimer@01c20c00 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun4i-a10-timer\";\n"
  "> +\t\t\treg = <0x01c20c00 0xa0>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,\n"
@@ -907,13 +919,13 @@
  "> +\t\t\tclocks = <&osc24M>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\twdt0: watchdog at 01c20ca0 {\n"
+ "> +\t\twdt0: watchdog@01c20ca0 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-wdt\";\n"
  "> +\t\t\treg = <0x01c20ca0 0x20>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tuart0: serial at 01c28000 {\n"
+ "> +\t\tuart0: serial@01c28000 {\n"
  "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> +\t\t\treg = <0x01c28000 0x400>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -926,7 +938,7 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tuart1: serial at 01c28400 {\n"
+ "> +\t\tuart1: serial@01c28400 {\n"
  "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> +\t\t\treg = <0x01c28400 0x400>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -939,7 +951,7 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tuart2: serial at 01c28800 {\n"
+ "> +\t\tuart2: serial@01c28800 {\n"
  "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> +\t\t\treg = <0x01c28800 0x400>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -952,7 +964,7 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tuart3: serial at 01c28c00 {\n"
+ "> +\t\tuart3: serial@01c28c00 {\n"
  "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> +\t\t\treg = <0x01c28c00 0x400>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -965,7 +977,7 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\ti2c0: i2c at 01c2ac00 {\n"
+ "> +\t\ti2c0: i2c@01c2ac00 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n"
  "> +\t\t\treg = <0x01c2ac00 0x400>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -976,7 +988,7 @@
  "> +\t\t\t#size-cells = <0>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\ti2c1: i2c at 01c2b000 {\n"
+ "> +\t\ti2c1: i2c@01c2b000 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n"
  "> +\t\t\treg = <0x01c2b000 0x400>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -987,7 +999,7 @@
  "> +\t\t\t#size-cells = <0>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\ti2c2: i2c at 01c2b400 {\n"
+ "> +\t\ti2c2: i2c@01c2b400 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n"
  "> +\t\t\treg = <0x01c2b400 0x400>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -998,7 +1010,7 @@
  "> +\t\t\t#size-cells = <0>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tgic: interrupt-controller at 01c81000 {\n"
+ "> +\t\tgic: interrupt-controller@01c81000 {\n"
  "> +\t\t\tcompatible = \"arm,cortex-a7-gic\", \"arm,cortex-a15-gic\";\n"
  "> +\t\t\treg = <0x01c81000 0x1000>,\n"
  "> +\t\t\t      <0x01c82000 0x1000>,\n"
@@ -1009,14 +1021,14 @@
  "> +\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\trtc: rtc at 01f00000 {\n"
+ "> +\t\trtc: rtc@01f00000 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-rtc\";\n"
  "> +\t\t\treg = <0x01f00000 0x54>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,\n"
  "> +\t\t\t\t     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tprcm at 01f01400 {\n"
+ "> +\t\tprcm@01f01400 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun8i-a23-prcm\";\n"
  "> +\t\t\treg = <0x01f01400 0x200>;\n"
  "> +\n"
@@ -1060,12 +1072,12 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tcpucfg at 01f01c00 {\n"
+ "> +\t\tcpucfg@01f01c00 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun8i-a23-cpuconfig\";\n"
  "> +\t\t\treg = <0x01f01c00 0x300>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tr_uart: serial at 01f02800 {\n"
+ "> +\t\tr_uart: serial@01f02800 {\n"
  "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> +\t\t\treg = <0x01f02800 0x400>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -1076,7 +1088,7 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tr_pio: pinctrl at 01f02c00 {\n"
+ "> +\t\tr_pio: pinctrl@01f02c00 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun8i-a23-r-pinctrl\";\n"
  "> +\t\t\treg = <0x01f02c00 0x400>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -1088,7 +1100,7 @@
  "> +\t\t\t#size-cells = <0>;\n"
  "> +\t\t\t#gpio-cells = <3>;\n"
  "> +\n"
- "> +\t\t\tr_uart_pins_a: r_uart at 0 {\n"
+ "> +\t\t\tr_uart_pins_a: r_uart@0 {\n"
  "> +\t\t\t\tallwinner,pins = \"PL2\", \"PL3\";\n"
  "> +\t\t\t\tallwinner,function = \"s_uart\";\n"
  "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n"
@@ -1099,4 +1111,4 @@
  "> +};\n"
  >
 
-1559f4216d6c7006066f02d496048990865e2941500a216d70ad60a4d50be5cd
+d3aaab37ad32f4c0313fbe456aed55c5867f1045853aaeae47c84ea06f44d52d

diff --git a/a/1.txt b/N2/1.txt
index 709f1ff..2222b90 100644
--- a/a/1.txt
+++ b/N2/1.txt
@@ -109,7 +109,7 @@ Hans
 > -		#size-cells = <1>;
 > -		ranges;
 > -
-> -		framebuffer at 0 {
+> -		framebuffer@0 {
 > -			compatible = "allwinner,simple-framebuffer",
 > -				     "simple-framebuffer";
 > -			allwinner,pipeline = "de_be0-lcd0";
@@ -156,7 +156,7 @@ Hans
 > -			clock-output-names = "osc32k";
 > -		};
 > -
-> -		pll1: clk at 01c20000 {
+> -		pll1: clk@01c20000 {
 > -			#clock-cells = <0>;
 > -			compatible = "allwinner,sun8i-a23-pll1-clk";
 > -			reg = <0x01c20000 0x4>;
@@ -171,7 +171,7 @@ Hans
 >   			clock-output-names = "pll5";
 >   		};
 >
-> -		pll6: clk at 01c20028 {
+> -		pll6: clk@01c20028 {
 > -			#clock-cells = <1>;
 > -			compatible = "allwinner,sun6i-a31-pll6-clk";
 > -			reg = <0x01c20028 0x4>;
@@ -179,7 +179,7 @@ Hans
 > -			clock-output-names = "pll6", "pll6x2";
 > -		};
 > -
-> -		cpu: cpu_clk at 01c20050 {
+> -		cpu: cpu_clk@01c20050 {
 > -			#clock-cells = <0>;
 > -			compatible = "allwinner,sun4i-a10-cpu-clk";
 > -			reg = <0x01c20050 0x4>;
@@ -194,14 +194,14 @@ Hans
 > -			clock-output-names = "cpu";
 > -		};
 > -
->   		axi: axi_clk at 01c20050 {
+>   		axi: axi_clk@01c20050 {
 >   			#clock-cells = <0>;
 >   			compatible = "allwinner,sun8i-a23-axi-clk";
 > @@ -168,22 +85,6 @@
 >   			clock-output-names = "axi";
 >   		};
 >
-> -		ahb1: ahb1_clk at 01c20054 {
+> -		ahb1: ahb1_clk@01c20054 {
 > -			#clock-cells = <0>;
 > -			compatible = "allwinner,sun6i-a31-ahb1-clk";
 > -			reg = <0x01c20054 0x4>;
@@ -209,7 +209,7 @@ Hans
 > -			clock-output-names = "ahb1";
 > -		};
 > -
-> -		apb1: apb1_clk at 01c20054 {
+> -		apb1: apb1_clk@01c20054 {
 > -			#clock-cells = <0>;
 > -			compatible = "allwinner,sun4i-a10-apb0-clk";
 > -			reg = <0x01c20054 0x4>;
@@ -217,14 +217,14 @@ Hans
 > -			clock-output-names = "apb1";
 > -		};
 > -
->   		ahb1_gates: clk at 01c20060 {
+>   		ahb1_gates: clk@01c20060 {
 >   			#clock-cells = <1>;
 >   			compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
 > @@ -228,36 +129,6 @@
 >   					"apb2_uart3", "apb2_uart4";
 >   		};
 >
-> -		mmc0_clk: clk at 01c20088 {
+> -		mmc0_clk: clk@01c20088 {
 > -			#clock-cells = <1>;
 > -			compatible = "allwinner,sun4i-a10-mmc-clk";
 > -			reg = <0x01c20088 0x4>;
@@ -234,7 +234,7 @@ Hans
 > -					     "mmc0_sample";
 > -		};
 > -
-> -		mmc1_clk: clk at 01c2008c {
+> -		mmc1_clk: clk@01c2008c {
 > -			#clock-cells = <1>;
 > -			compatible = "allwinner,sun4i-a10-mmc-clk";
 > -			reg = <0x01c2008c 0x4>;
@@ -244,7 +244,7 @@ Hans
 > -					     "mmc1_sample";
 > -		};
 > -
-> -		mmc2_clk: clk at 01c20090 {
+> -		mmc2_clk: clk@01c20090 {
 > -			#clock-cells = <1>;
 > -			compatible = "allwinner,sun4i-a10-mmc-clk";
 > -			reg = <0x01c20090 0x4>;
@@ -254,26 +254,26 @@ Hans
 > -					     "mmc2_sample";
 > -		};
 > -
->   		mbus_clk: clk at 01c2015c {
+>   		mbus_clk: clk@01c2015c {
 >   			#clock-cells = <0>;
 >   			compatible = "allwinner,sun8i-a23-mbus-clk";
 > @@ -268,11 +139,6 @@
 >   	};
 >
->   	soc at 01c00000 {
+>   	soc@01c00000 {
 > -		compatible = "simple-bus";
 > -		#address-cells = <1>;
 > -		#size-cells = <1>;
 > -		ranges;
 > -
->   		dma: dma-controller at 01c02000 {
+>   		dma: dma-controller@01c02000 {
 >   			compatible = "allwinner,sun8i-a23-dma";
 >   			reg = <0x01c02000 0x1000>;
 > @@ -282,75 +148,12 @@
 >   			#dma-cells = <1>;
 >   		};
 >
-> -		mmc0: mmc at 01c0f000 {
+> -		mmc0: mmc@01c0f000 {
 > -			compatible = "allwinner,sun5i-a13-mmc";
 > -			reg = <0x01c0f000 0x1000>;
 > -			clocks = <&ahb1_gates 8>,
@@ -292,7 +292,7 @@ Hans
 > -			#size-cells = <0>;
 > -		};
 > -
-> -		mmc1: mmc at 01c10000 {
+> -		mmc1: mmc@01c10000 {
 > -			compatible = "allwinner,sun5i-a13-mmc";
 > -			reg = <0x01c10000 0x1000>;
 > -			clocks = <&ahb1_gates 9>,
@@ -311,7 +311,7 @@ Hans
 > -			#size-cells = <0>;
 > -		};
 > -
-> -		mmc2: mmc at 01c11000 {
+> -		mmc2: mmc@01c11000 {
 > -			compatible = "allwinner,sun5i-a13-mmc";
 > -			reg = <0x01c11000 0x1000>;
 > -			clocks = <&ahb1_gates 10>,
@@ -330,7 +330,7 @@ Hans
 > -			#size-cells = <0>;
 > -		};
 > -
->   		pio: pinctrl at 01c20800 {
+>   		pio: pinctrl@01c20800 {
 >   			compatible = "allwinner,sun8i-a23-pinctrl";
 > -			reg = <0x01c20800 0x400>;
 >   			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
@@ -344,52 +344,52 @@ Hans
 > -			#gpio-cells = <3>;
 > +
 >
->   			uart0_pins_a: uart0 at 0 {
+>   			uart0_pins_a: uart0@0 {
 >   				allwinner,pins = "PF2", "PF4";
 > @@ -359,20 +162,6 @@
 >   				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 >   			};
 >
-> -			mmc0_pins_a: mmc0 at 0 {
+> -			mmc0_pins_a: mmc0@0 {
 > -				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 > -				allwinner,function = "mmc0";
 > -				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 > -				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 > -			};
 > -
-> -			mmc1_pins_a: mmc1 at 0 {
+> -			mmc1_pins_a: mmc1@0 {
 > -				allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
 > -				allwinner,function = "mmc1";
 > -				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 > -				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 > -			};
 > -
->   			i2c0_pins_a: i2c0 at 0 {
+>   			i2c0_pins_a: i2c0@0 {
 >   				allwinner,pins = "PH2", "PH3";
 >   				allwinner,function = "i2c0";
 > @@ -395,38 +184,6 @@
 >   			};
 >   		};
 >
-> -		ahb1_rst: reset at 01c202c0 {
+> -		ahb1_rst: reset@01c202c0 {
 > -			#reset-cells = <1>;
 > -			compatible = "allwinner,sun6i-a31-clock-reset";
 > -			reg = <0x01c202c0 0xc>;
 > -		};
 > -
-> -		apb1_rst: reset at 01c202d0 {
+> -		apb1_rst: reset@01c202d0 {
 > -			#reset-cells = <1>;
 > -			compatible = "allwinner,sun6i-a31-clock-reset";
 > -			reg = <0x01c202d0 0x4>;
 > -		};
 > -
-> -		apb2_rst: reset at 01c202d8 {
+> -		apb2_rst: reset@01c202d8 {
 > -			#reset-cells = <1>;
 > -			compatible = "allwinner,sun6i-a31-clock-reset";
 > -			reg = <0x01c202d8 0x4>;
 > -		};
 > -
-> -		timer at 01c20c00 {
+> -		timer@01c20c00 {
 > -			compatible = "allwinner,sun4i-a10-timer";
 > -			reg = <0x01c20c00 0xa0>;
 > -			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
@@ -397,20 +397,20 @@ Hans
 > -			clocks = <&osc24M>;
 > -		};
 > -
-> -		wdt0: watchdog at 01c20ca0 {
+> -		wdt0: watchdog@01c20ca0 {
 > -			compatible = "allwinner,sun6i-a31-wdt";
 > -			reg = <0x01c20ca0 0x20>;
 > -			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 > -		};
 > -
->   		lradc: lradc at 01c22800 {
+>   		lradc: lradc@01c22800 {
 >   			compatible = "allwinner,sun4i-a10-lradc-keys";
 >   			reg = <0x01c22800 0x100>;
 > @@ -434,58 +191,6 @@
 >   			status = "disabled";
 >   		};
 >
-> -		uart0: serial at 01c28000 {
+> -		uart0: serial@01c28000 {
 > -			compatible = "snps,dw-apb-uart";
 > -			reg = <0x01c28000 0x400>;
 > -			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
@@ -423,7 +423,7 @@ Hans
 > -			status = "disabled";
 > -		};
 > -
-> -		uart1: serial at 01c28400 {
+> -		uart1: serial@01c28400 {
 > -			compatible = "snps,dw-apb-uart";
 > -			reg = <0x01c28400 0x400>;
 > -			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
@@ -436,7 +436,7 @@ Hans
 > -			status = "disabled";
 > -		};
 > -
-> -		uart2: serial at 01c28800 {
+> -		uart2: serial@01c28800 {
 > -			compatible = "snps,dw-apb-uart";
 > -			reg = <0x01c28800 0x400>;
 > -			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -449,7 +449,7 @@ Hans
 > -			status = "disabled";
 > -		};
 > -
-> -		uart3: serial at 01c28c00 {
+> -		uart3: serial@01c28c00 {
 > -			compatible = "snps,dw-apb-uart";
 > -			reg = <0x01c28c00 0x400>;
 > -			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
@@ -462,7 +462,7 @@ Hans
 > -			status = "disabled";
 > -		};
 > -
->   		uart4: serial at 01c29000 {
+>   		uart4: serial@01c29000 {
 >   			compatible = "snps,dw-apb-uart";
 >   			reg = <0x01c29000 0x400>;
 > @@ -498,136 +203,5 @@
@@ -470,7 +470,7 @@ Hans
 >   			status = "disabled";
 >   		};
 > -
-> -		i2c0: i2c at 01c2ac00 {
+> -		i2c0: i2c@01c2ac00 {
 > -			compatible = "allwinner,sun6i-a31-i2c";
 > -			reg = <0x01c2ac00 0x400>;
 > -			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
@@ -481,7 +481,7 @@ Hans
 > -			#size-cells = <0>;
 > -		};
 > -
-> -		i2c1: i2c at 01c2b000 {
+> -		i2c1: i2c@01c2b000 {
 > -			compatible = "allwinner,sun6i-a31-i2c";
 > -			reg = <0x01c2b000 0x400>;
 > -			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
@@ -492,7 +492,7 @@ Hans
 > -			#size-cells = <0>;
 > -		};
 > -
-> -		i2c2: i2c at 01c2b400 {
+> -		i2c2: i2c@01c2b400 {
 > -			compatible = "allwinner,sun6i-a31-i2c";
 > -			reg = <0x01c2b400 0x400>;
 > -			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
@@ -503,7 +503,7 @@ Hans
 > -			#size-cells = <0>;
 > -		};
 > -
-> -		gic: interrupt-controller at 01c81000 {
+> -		gic: interrupt-controller@01c81000 {
 > -			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 > -			reg = <0x01c81000 0x1000>,
 > -			      <0x01c82000 0x1000>,
@@ -514,14 +514,14 @@ Hans
 > -			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 > -		};
 > -
-> -		rtc: rtc at 01f00000 {
+> -		rtc: rtc@01f00000 {
 > -			compatible = "allwinner,sun6i-a31-rtc";
 > -			reg = <0x01f00000 0x54>;
 > -			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 > -				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 > -		};
 > -
-> -		prcm at 01f01400 {
+> -		prcm@01f01400 {
 > -			compatible = "allwinner,sun8i-a23-prcm";
 > -			reg = <0x01f01400 0x200>;
 > -
@@ -565,12 +565,12 @@ Hans
 > -			};
 > -		};
 > -
-> -		cpucfg at 01f01c00 {
+> -		cpucfg@01f01c00 {
 > -			compatible = "allwinner,sun8i-a23-cpuconfig";
 > -			reg = <0x01f01c00 0x300>;
 > -		};
 > -
-> -		r_uart: serial at 01f02800 {
+> -		r_uart: serial@01f02800 {
 > -			compatible = "snps,dw-apb-uart";
 > -			reg = <0x01f02800 0x400>;
 > -			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
@@ -581,7 +581,7 @@ Hans
 > -			status = "disabled";
 > -		};
 > -
-> -		r_pio: pinctrl at 01f02c00 {
+> -		r_pio: pinctrl@01f02c00 {
 > -			compatible = "allwinner,sun8i-a23-r-pinctrl";
 > -			reg = <0x01f02c00 0x400>;
 > -			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
@@ -593,7 +593,7 @@ Hans
 > -			#size-cells = <0>;
 > -			#gpio-cells = <3>;
 > -
-> -			r_uart_pins_a: r_uart at 0 {
+> -			r_uart_pins_a: r_uart@0 {
 > -				allwinner,pins = "PL2", "PL3";
 > -				allwinner,function = "s_uart";
 > -				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
@@ -667,7 +667,7 @@ Hans
 > +		#size-cells = <1>;
 > +		ranges;
 > +
-> +		framebuffer at 0 {
+> +		framebuffer@0 {
 > +			compatible = "allwinner,simple-framebuffer",
 > +				     "simple-framebuffer";
 > +			allwinner,pipeline = "de_be0-lcd0";
@@ -705,7 +705,7 @@ Hans
 > +			clock-output-names = "osc32k";
 > +		};
 > +
-> +		pll1: clk at 01c20000 {
+> +		pll1: clk@01c20000 {
 > +			#clock-cells = <0>;
 > +			compatible = "allwinner,sun8i-a23-pll1-clk";
 > +			reg = <0x01c20000 0x4>;
@@ -713,7 +713,7 @@ Hans
 > +			clock-output-names = "pll1";
 > +		};
 > +
-> +		pll6: clk at 01c20028 {
+> +		pll6: clk@01c20028 {
 > +			#clock-cells = <1>;
 > +			compatible = "allwinner,sun6i-a31-pll6-clk";
 > +			reg = <0x01c20028 0x4>;
@@ -721,7 +721,7 @@ Hans
 > +			clock-output-names = "pll6", "pll6x2";
 > +		};
 > +
-> +		cpu: cpu_clk at 01c20050 {
+> +		cpu: cpu_clk@01c20050 {
 > +			#clock-cells = <0>;
 > +			compatible = "allwinner,sun4i-a10-cpu-clk";
 > +			reg = <0x01c20050 0x4>;
@@ -737,7 +737,7 @@ Hans
 > +		};
 > +
 > +
-> +		ahb1: ahb1_clk at 01c20054 {
+> +		ahb1: ahb1_clk@01c20054 {
 > +			#clock-cells = <0>;
 > +			compatible = "allwinner,sun6i-a31-ahb1-clk";
 > +			reg = <0x01c20054 0x4>;
@@ -745,7 +745,7 @@ Hans
 > +			clock-output-names = "ahb1";
 > +		};
 > +
-> +		apb1: apb1_clk at 01c20054 {
+> +		apb1: apb1_clk@01c20054 {
 > +			#clock-cells = <0>;
 > +			compatible = "allwinner,sun4i-a10-apb0-clk";
 > +			reg = <0x01c20054 0x4>;
@@ -753,7 +753,7 @@ Hans
 > +			clock-output-names = "apb1";
 > +		};
 > +
-> +		mmc0_clk: clk at 01c20088 {
+> +		mmc0_clk: clk@01c20088 {
 > +			#clock-cells = <1>;
 > +			compatible = "allwinner,sun4i-a10-mmc-clk";
 > +			reg = <0x01c20088 0x4>;
@@ -763,7 +763,7 @@ Hans
 > +					     "mmc0_sample";
 > +		};
 > +
-> +		mmc1_clk: clk at 01c2008c {
+> +		mmc1_clk: clk@01c2008c {
 > +			#clock-cells = <1>;
 > +			compatible = "allwinner,sun4i-a10-mmc-clk";
 > +			reg = <0x01c2008c 0x4>;
@@ -773,7 +773,7 @@ Hans
 > +					     "mmc1_sample";
 > +		};
 > +
-> +		mmc2_clk: clk at 01c20090 {
+> +		mmc2_clk: clk@01c20090 {
 > +			#clock-cells = <1>;
 > +			compatible = "allwinner,sun4i-a10-mmc-clk";
 > +			reg = <0x01c20090 0x4>;
@@ -785,14 +785,14 @@ Hans
 > +
 > +	};
 > +
-> +	soc at 01c00000 {
+> +	soc@01c00000 {
 > +		compatible = "simple-bus";
 > +		#address-cells = <1>;
 > +		#size-cells = <1>;
 > +		ranges;
 > +
 > +
-> +		mmc0: mmc at 01c0f000 {
+> +		mmc0: mmc@01c0f000 {
 > +			compatible = "allwinner,sun5i-a13-mmc";
 > +			reg = <0x01c0f000 0x1000>;
 > +			clocks = <&ahb1_gates 8>,
@@ -811,7 +811,7 @@ Hans
 > +			#size-cells = <0>;
 > +		};
 > +
-> +		mmc1: mmc at 01c10000 {
+> +		mmc1: mmc@01c10000 {
 > +			compatible = "allwinner,sun5i-a13-mmc";
 > +			reg = <0x01c10000 0x1000>;
 > +			clocks = <&ahb1_gates 9>,
@@ -830,7 +830,7 @@ Hans
 > +			#size-cells = <0>;
 > +		};
 > +
-> +		mmc2: mmc at 01c11000 {
+> +		mmc2: mmc@01c11000 {
 > +			compatible = "allwinner,sun5i-a13-mmc";
 > +			reg = <0x01c11000 0x1000>;
 > +			clocks = <&ahb1_gates 10>,
@@ -849,7 +849,7 @@ Hans
 > +			#size-cells = <0>;
 > +		};
 > +
-> +		pio: pinctrl at 01c20800 {
+> +		pio: pinctrl@01c20800 {
 > +			reg = <0x01c20800 0x400>;
 > +			clocks = <&apb1_gates 5>;
 > +			gpio-controller;
@@ -858,14 +858,14 @@ Hans
 > +			#size-cells = <0>;
 > +			#gpio-cells = <3>;
 > +
-> +			mmc0_pins_a: mmc0 at 0 {
+> +			mmc0_pins_a: mmc0@0 {
 > +				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 > +				allwinner,function = "mmc0";
 > +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 > +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 > +			};
 > +
-> +			mmc1_pins_a: mmc1 at 0 {
+> +			mmc1_pins_a: mmc1@0 {
 > +				allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
 > +				allwinner,function = "mmc1";
 > +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
@@ -873,25 +873,25 @@ Hans
 > +			};
 > +		};
 > +
-> +		ahb1_rst: reset at 01c202c0 {
+> +		ahb1_rst: reset@01c202c0 {
 > +			#reset-cells = <1>;
 > +			compatible = "allwinner,sun6i-a31-clock-reset";
 > +			reg = <0x01c202c0 0xc>;
 > +		};
 > +
-> +		apb1_rst: reset at 01c202d0 {
+> +		apb1_rst: reset@01c202d0 {
 > +			#reset-cells = <1>;
 > +			compatible = "allwinner,sun6i-a31-clock-reset";
 > +			reg = <0x01c202d0 0x4>;
 > +		};
 > +
-> +		apb2_rst: reset at 01c202d8 {
+> +		apb2_rst: reset@01c202d8 {
 > +			#reset-cells = <1>;
 > +			compatible = "allwinner,sun6i-a31-clock-reset";
 > +			reg = <0x01c202d8 0x4>;
 > +		};
 > +
-> +		timer at 01c20c00 {
+> +		timer@01c20c00 {
 > +			compatible = "allwinner,sun4i-a10-timer";
 > +			reg = <0x01c20c00 0xa0>;
 > +			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
@@ -899,13 +899,13 @@ Hans
 > +			clocks = <&osc24M>;
 > +		};
 > +
-> +		wdt0: watchdog at 01c20ca0 {
+> +		wdt0: watchdog@01c20ca0 {
 > +			compatible = "allwinner,sun6i-a31-wdt";
 > +			reg = <0x01c20ca0 0x20>;
 > +			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 > +		};
 > +
-> +		uart0: serial at 01c28000 {
+> +		uart0: serial@01c28000 {
 > +			compatible = "snps,dw-apb-uart";
 > +			reg = <0x01c28000 0x400>;
 > +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
@@ -918,7 +918,7 @@ Hans
 > +			status = "disabled";
 > +		};
 > +
-> +		uart1: serial at 01c28400 {
+> +		uart1: serial@01c28400 {
 > +			compatible = "snps,dw-apb-uart";
 > +			reg = <0x01c28400 0x400>;
 > +			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
@@ -931,7 +931,7 @@ Hans
 > +			status = "disabled";
 > +		};
 > +
-> +		uart2: serial at 01c28800 {
+> +		uart2: serial@01c28800 {
 > +			compatible = "snps,dw-apb-uart";
 > +			reg = <0x01c28800 0x400>;
 > +			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -944,7 +944,7 @@ Hans
 > +			status = "disabled";
 > +		};
 > +
-> +		uart3: serial at 01c28c00 {
+> +		uart3: serial@01c28c00 {
 > +			compatible = "snps,dw-apb-uart";
 > +			reg = <0x01c28c00 0x400>;
 > +			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
@@ -957,7 +957,7 @@ Hans
 > +			status = "disabled";
 > +		};
 > +
-> +		i2c0: i2c at 01c2ac00 {
+> +		i2c0: i2c@01c2ac00 {
 > +			compatible = "allwinner,sun6i-a31-i2c";
 > +			reg = <0x01c2ac00 0x400>;
 > +			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
@@ -968,7 +968,7 @@ Hans
 > +			#size-cells = <0>;
 > +		};
 > +
-> +		i2c1: i2c at 01c2b000 {
+> +		i2c1: i2c@01c2b000 {
 > +			compatible = "allwinner,sun6i-a31-i2c";
 > +			reg = <0x01c2b000 0x400>;
 > +			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
@@ -979,7 +979,7 @@ Hans
 > +			#size-cells = <0>;
 > +		};
 > +
-> +		i2c2: i2c at 01c2b400 {
+> +		i2c2: i2c@01c2b400 {
 > +			compatible = "allwinner,sun6i-a31-i2c";
 > +			reg = <0x01c2b400 0x400>;
 > +			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
@@ -990,7 +990,7 @@ Hans
 > +			#size-cells = <0>;
 > +		};
 > +
-> +		gic: interrupt-controller at 01c81000 {
+> +		gic: interrupt-controller@01c81000 {
 > +			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 > +			reg = <0x01c81000 0x1000>,
 > +			      <0x01c82000 0x1000>,
@@ -1001,14 +1001,14 @@ Hans
 > +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 > +		};
 > +
-> +		rtc: rtc at 01f00000 {
+> +		rtc: rtc@01f00000 {
 > +			compatible = "allwinner,sun6i-a31-rtc";
 > +			reg = <0x01f00000 0x54>;
 > +			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 > +				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 > +		};
 > +
-> +		prcm at 01f01400 {
+> +		prcm@01f01400 {
 > +			compatible = "allwinner,sun8i-a23-prcm";
 > +			reg = <0x01f01400 0x200>;
 > +
@@ -1052,12 +1052,12 @@ Hans
 > +			};
 > +		};
 > +
-> +		cpucfg at 01f01c00 {
+> +		cpucfg@01f01c00 {
 > +			compatible = "allwinner,sun8i-a23-cpuconfig";
 > +			reg = <0x01f01c00 0x300>;
 > +		};
 > +
-> +		r_uart: serial at 01f02800 {
+> +		r_uart: serial@01f02800 {
 > +			compatible = "snps,dw-apb-uart";
 > +			reg = <0x01f02800 0x400>;
 > +			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
@@ -1068,7 +1068,7 @@ Hans
 > +			status = "disabled";
 > +		};
 > +
-> +		r_pio: pinctrl at 01f02c00 {
+> +		r_pio: pinctrl@01f02c00 {
 > +			compatible = "allwinner,sun8i-a23-r-pinctrl";
 > +			reg = <0x01f02c00 0x400>;
 > +			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
@@ -1080,7 +1080,7 @@ Hans
 > +			#size-cells = <0>;
 > +			#gpio-cells = <3>;
 > +
-> +			r_uart_pins_a: r_uart at 0 {
+> +			r_uart_pins_a: r_uart@0 {
 > +				allwinner,pins = "PL2", "PL3";
 > +				allwinner,function = "s_uart";
 > +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
diff --git a/a/content_digest b/N2/content_digest
index 1e3e94e..f913b10 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -1,9 +1,20 @@
  "ref\01431240383-12763-1-git-send-email-vishnupatekar0510@gmail.com\0"
  "ref\01431240383-12763-5-git-send-email-vishnupatekar0510@gmail.com\0"
- "From\0hdegoede@redhat.com (Hans de Goede)\0"
- "Subject\0[PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi\0"
+ "From\0Hans de Goede <hdegoede@redhat.com>\0"
+ "Subject\0Re: [PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi\0"
  "Date\0Sun, 10 May 2015 10:52:38 +0200\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
+ "To\0Vishnu Patekar <vishnupatekar0510@gmail.com>"
+  maxime.ripard@free-electrons.com
+  emilio@elopez.com.ar
+  linus.walleij@linaro.org
+ " robh+dt@kernel.org\0"
+ "Cc\0wens@csie.org"
+  jenskuske@gmail.com
+  arnd@arndb.de
+  linux-arm-kernel@lists.infradead.org
+  linux-kernel@vger.kernel.org
+  linux-sunxi@googlegroups.com
+ " devicetree@vger.kernel.org\0"
  "\00:1\0"
  "b\0"
  "Hi,\n"
@@ -117,7 +128,7 @@
  "> -\t\t#size-cells = <1>;\n"
  "> -\t\tranges;\n"
  "> -\n"
- "> -\t\tframebuffer at 0 {\n"
+ "> -\t\tframebuffer@0 {\n"
  "> -\t\t\tcompatible = \"allwinner,simple-framebuffer\",\n"
  "> -\t\t\t\t     \"simple-framebuffer\";\n"
  "> -\t\t\tallwinner,pipeline = \"de_be0-lcd0\";\n"
@@ -164,7 +175,7 @@
  "> -\t\t\tclock-output-names = \"osc32k\";\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tpll1: clk at 01c20000 {\n"
+ "> -\t\tpll1: clk@01c20000 {\n"
  "> -\t\t\t#clock-cells = <0>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n"
  "> -\t\t\treg = <0x01c20000 0x4>;\n"
@@ -179,7 +190,7 @@
  ">   \t\t\tclock-output-names = \"pll5\";\n"
  ">   \t\t};\n"
  ">\n"
- "> -\t\tpll6: clk at 01c20028 {\n"
+ "> -\t\tpll6: clk@01c20028 {\n"
  "> -\t\t\t#clock-cells = <1>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n"
  "> -\t\t\treg = <0x01c20028 0x4>;\n"
@@ -187,7 +198,7 @@
  "> -\t\t\tclock-output-names = \"pll6\", \"pll6x2\";\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tcpu: cpu_clk at 01c20050 {\n"
+ "> -\t\tcpu: cpu_clk@01c20050 {\n"
  "> -\t\t\t#clock-cells = <0>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n"
  "> -\t\t\treg = <0x01c20050 0x4>;\n"
@@ -202,14 +213,14 @@
  "> -\t\t\tclock-output-names = \"cpu\";\n"
  "> -\t\t};\n"
  "> -\n"
- ">   \t\taxi: axi_clk at 01c20050 {\n"
+ ">   \t\taxi: axi_clk@01c20050 {\n"
  ">   \t\t\t#clock-cells = <0>;\n"
  ">   \t\t\tcompatible = \"allwinner,sun8i-a23-axi-clk\";\n"
  "> @@ -168,22 +85,6 @@\n"
  ">   \t\t\tclock-output-names = \"axi\";\n"
  ">   \t\t};\n"
  ">\n"
- "> -\t\tahb1: ahb1_clk at 01c20054 {\n"
+ "> -\t\tahb1: ahb1_clk@01c20054 {\n"
  "> -\t\t\t#clock-cells = <0>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n"
  "> -\t\t\treg = <0x01c20054 0x4>;\n"
@@ -217,7 +228,7 @@
  "> -\t\t\tclock-output-names = \"ahb1\";\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tapb1: apb1_clk at 01c20054 {\n"
+ "> -\t\tapb1: apb1_clk@01c20054 {\n"
  "> -\t\t\t#clock-cells = <0>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n"
  "> -\t\t\treg = <0x01c20054 0x4>;\n"
@@ -225,14 +236,14 @@
  "> -\t\t\tclock-output-names = \"apb1\";\n"
  "> -\t\t};\n"
  "> -\n"
- ">   \t\tahb1_gates: clk at 01c20060 {\n"
+ ">   \t\tahb1_gates: clk@01c20060 {\n"
  ">   \t\t\t#clock-cells = <1>;\n"
  ">   \t\t\tcompatible = \"allwinner,sun8i-a23-ahb1-gates-clk\";\n"
  "> @@ -228,36 +129,6 @@\n"
  ">   \t\t\t\t\t\"apb2_uart3\", \"apb2_uart4\";\n"
  ">   \t\t};\n"
  ">\n"
- "> -\t\tmmc0_clk: clk at 01c20088 {\n"
+ "> -\t\tmmc0_clk: clk@01c20088 {\n"
  "> -\t\t\t#clock-cells = <1>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n"
  "> -\t\t\treg = <0x01c20088 0x4>;\n"
@@ -242,7 +253,7 @@
  "> -\t\t\t\t\t     \"mmc0_sample\";\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tmmc1_clk: clk at 01c2008c {\n"
+ "> -\t\tmmc1_clk: clk@01c2008c {\n"
  "> -\t\t\t#clock-cells = <1>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n"
  "> -\t\t\treg = <0x01c2008c 0x4>;\n"
@@ -252,7 +263,7 @@
  "> -\t\t\t\t\t     \"mmc1_sample\";\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tmmc2_clk: clk at 01c20090 {\n"
+ "> -\t\tmmc2_clk: clk@01c20090 {\n"
  "> -\t\t\t#clock-cells = <1>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n"
  "> -\t\t\treg = <0x01c20090 0x4>;\n"
@@ -262,26 +273,26 @@
  "> -\t\t\t\t\t     \"mmc2_sample\";\n"
  "> -\t\t};\n"
  "> -\n"
- ">   \t\tmbus_clk: clk at 01c2015c {\n"
+ ">   \t\tmbus_clk: clk@01c2015c {\n"
  ">   \t\t\t#clock-cells = <0>;\n"
  ">   \t\t\tcompatible = \"allwinner,sun8i-a23-mbus-clk\";\n"
  "> @@ -268,11 +139,6 @@\n"
  ">   \t};\n"
  ">\n"
- ">   \tsoc at 01c00000 {\n"
+ ">   \tsoc@01c00000 {\n"
  "> -\t\tcompatible = \"simple-bus\";\n"
  "> -\t\t#address-cells = <1>;\n"
  "> -\t\t#size-cells = <1>;\n"
  "> -\t\tranges;\n"
  "> -\n"
- ">   \t\tdma: dma-controller at 01c02000 {\n"
+ ">   \t\tdma: dma-controller@01c02000 {\n"
  ">   \t\t\tcompatible = \"allwinner,sun8i-a23-dma\";\n"
  ">   \t\t\treg = <0x01c02000 0x1000>;\n"
  "> @@ -282,75 +148,12 @@\n"
  ">   \t\t\t#dma-cells = <1>;\n"
  ">   \t\t};\n"
  ">\n"
- "> -\t\tmmc0: mmc at 01c0f000 {\n"
+ "> -\t\tmmc0: mmc@01c0f000 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n"
  "> -\t\t\treg = <0x01c0f000 0x1000>;\n"
  "> -\t\t\tclocks = <&ahb1_gates 8>,\n"
@@ -300,7 +311,7 @@
  "> -\t\t\t#size-cells = <0>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tmmc1: mmc at 01c10000 {\n"
+ "> -\t\tmmc1: mmc@01c10000 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n"
  "> -\t\t\treg = <0x01c10000 0x1000>;\n"
  "> -\t\t\tclocks = <&ahb1_gates 9>,\n"
@@ -319,7 +330,7 @@
  "> -\t\t\t#size-cells = <0>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tmmc2: mmc at 01c11000 {\n"
+ "> -\t\tmmc2: mmc@01c11000 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n"
  "> -\t\t\treg = <0x01c11000 0x1000>;\n"
  "> -\t\t\tclocks = <&ahb1_gates 10>,\n"
@@ -338,7 +349,7 @@
  "> -\t\t\t#size-cells = <0>;\n"
  "> -\t\t};\n"
  "> -\n"
- ">   \t\tpio: pinctrl at 01c20800 {\n"
+ ">   \t\tpio: pinctrl@01c20800 {\n"
  ">   \t\t\tcompatible = \"allwinner,sun8i-a23-pinctrl\";\n"
  "> -\t\t\treg = <0x01c20800 0x400>;\n"
  ">   \t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n"
@@ -352,52 +363,52 @@
  "> -\t\t\t#gpio-cells = <3>;\n"
  "> +\n"
  ">\n"
- ">   \t\t\tuart0_pins_a: uart0 at 0 {\n"
+ ">   \t\t\tuart0_pins_a: uart0@0 {\n"
  ">   \t\t\t\tallwinner,pins = \"PF2\", \"PF4\";\n"
  "> @@ -359,20 +162,6 @@\n"
  ">   \t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n"
  ">   \t\t\t};\n"
  ">\n"
- "> -\t\t\tmmc0_pins_a: mmc0 at 0 {\n"
+ "> -\t\t\tmmc0_pins_a: mmc0@0 {\n"
  "> -\t\t\t\tallwinner,pins = \"PF0\",\"PF1\",\"PF2\",\"PF3\",\"PF4\",\"PF5\";\n"
  "> -\t\t\t\tallwinner,function = \"mmc0\";\n"
  "> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n"
  "> -\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n"
  "> -\t\t\t};\n"
  "> -\n"
- "> -\t\t\tmmc1_pins_a: mmc1 at 0 {\n"
+ "> -\t\t\tmmc1_pins_a: mmc1@0 {\n"
  "> -\t\t\t\tallwinner,pins = \"PG0\",\"PG1\",\"PG2\",\"PG3\",\"PG4\",\"PG5\";\n"
  "> -\t\t\t\tallwinner,function = \"mmc1\";\n"
  "> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n"
  "> -\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n"
  "> -\t\t\t};\n"
  "> -\n"
- ">   \t\t\ti2c0_pins_a: i2c0 at 0 {\n"
+ ">   \t\t\ti2c0_pins_a: i2c0@0 {\n"
  ">   \t\t\t\tallwinner,pins = \"PH2\", \"PH3\";\n"
  ">   \t\t\t\tallwinner,function = \"i2c0\";\n"
  "> @@ -395,38 +184,6 @@\n"
  ">   \t\t\t};\n"
  ">   \t\t};\n"
  ">\n"
- "> -\t\tahb1_rst: reset at 01c202c0 {\n"
+ "> -\t\tahb1_rst: reset@01c202c0 {\n"
  "> -\t\t\t#reset-cells = <1>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n"
  "> -\t\t\treg = <0x01c202c0 0xc>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tapb1_rst: reset at 01c202d0 {\n"
+ "> -\t\tapb1_rst: reset@01c202d0 {\n"
  "> -\t\t\t#reset-cells = <1>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n"
  "> -\t\t\treg = <0x01c202d0 0x4>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tapb2_rst: reset at 01c202d8 {\n"
+ "> -\t\tapb2_rst: reset@01c202d8 {\n"
  "> -\t\t\t#reset-cells = <1>;\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n"
  "> -\t\t\treg = <0x01c202d8 0x4>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\ttimer at 01c20c00 {\n"
+ "> -\t\ttimer@01c20c00 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun4i-a10-timer\";\n"
  "> -\t\t\treg = <0x01c20c00 0xa0>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,\n"
@@ -405,20 +416,20 @@
  "> -\t\t\tclocks = <&osc24M>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\twdt0: watchdog at 01c20ca0 {\n"
+ "> -\t\twdt0: watchdog@01c20ca0 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-wdt\";\n"
  "> -\t\t\treg = <0x01c20ca0 0x20>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;\n"
  "> -\t\t};\n"
  "> -\n"
- ">   \t\tlradc: lradc at 01c22800 {\n"
+ ">   \t\tlradc: lradc@01c22800 {\n"
  ">   \t\t\tcompatible = \"allwinner,sun4i-a10-lradc-keys\";\n"
  ">   \t\t\treg = <0x01c22800 0x100>;\n"
  "> @@ -434,58 +191,6 @@\n"
  ">   \t\t\tstatus = \"disabled\";\n"
  ">   \t\t};\n"
  ">\n"
- "> -\t\tuart0: serial at 01c28000 {\n"
+ "> -\t\tuart0: serial@01c28000 {\n"
  "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> -\t\t\treg = <0x01c28000 0x400>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -431,7 +442,7 @@
  "> -\t\t\tstatus = \"disabled\";\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tuart1: serial at 01c28400 {\n"
+ "> -\t\tuart1: serial@01c28400 {\n"
  "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> -\t\t\treg = <0x01c28400 0x400>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -444,7 +455,7 @@
  "> -\t\t\tstatus = \"disabled\";\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tuart2: serial at 01c28800 {\n"
+ "> -\t\tuart2: serial@01c28800 {\n"
  "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> -\t\t\treg = <0x01c28800 0x400>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -457,7 +468,7 @@
  "> -\t\t\tstatus = \"disabled\";\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tuart3: serial at 01c28c00 {\n"
+ "> -\t\tuart3: serial@01c28c00 {\n"
  "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> -\t\t\treg = <0x01c28c00 0x400>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -470,7 +481,7 @@
  "> -\t\t\tstatus = \"disabled\";\n"
  "> -\t\t};\n"
  "> -\n"
- ">   \t\tuart4: serial at 01c29000 {\n"
+ ">   \t\tuart4: serial@01c29000 {\n"
  ">   \t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  ">   \t\t\treg = <0x01c29000 0x400>;\n"
  "> @@ -498,136 +203,5 @@\n"
@@ -478,7 +489,7 @@
  ">   \t\t\tstatus = \"disabled\";\n"
  ">   \t\t};\n"
  "> -\n"
- "> -\t\ti2c0: i2c at 01c2ac00 {\n"
+ "> -\t\ti2c0: i2c@01c2ac00 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n"
  "> -\t\t\treg = <0x01c2ac00 0x400>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -489,7 +500,7 @@
  "> -\t\t\t#size-cells = <0>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\ti2c1: i2c at 01c2b000 {\n"
+ "> -\t\ti2c1: i2c@01c2b000 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n"
  "> -\t\t\treg = <0x01c2b000 0x400>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -500,7 +511,7 @@
  "> -\t\t\t#size-cells = <0>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\ti2c2: i2c at 01c2b400 {\n"
+ "> -\t\ti2c2: i2c@01c2b400 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n"
  "> -\t\t\treg = <0x01c2b400 0x400>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -511,7 +522,7 @@
  "> -\t\t\t#size-cells = <0>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tgic: interrupt-controller at 01c81000 {\n"
+ "> -\t\tgic: interrupt-controller@01c81000 {\n"
  "> -\t\t\tcompatible = \"arm,cortex-a7-gic\", \"arm,cortex-a15-gic\";\n"
  "> -\t\t\treg = <0x01c81000 0x1000>,\n"
  "> -\t\t\t      <0x01c82000 0x1000>,\n"
@@ -522,14 +533,14 @@
  "> -\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\trtc: rtc at 01f00000 {\n"
+ "> -\t\trtc: rtc@01f00000 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun6i-a31-rtc\";\n"
  "> -\t\t\treg = <0x01f00000 0x54>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,\n"
  "> -\t\t\t\t     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tprcm at 01f01400 {\n"
+ "> -\t\tprcm@01f01400 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun8i-a23-prcm\";\n"
  "> -\t\t\treg = <0x01f01400 0x200>;\n"
  "> -\n"
@@ -573,12 +584,12 @@
  "> -\t\t\t};\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tcpucfg at 01f01c00 {\n"
+ "> -\t\tcpucfg@01f01c00 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun8i-a23-cpuconfig\";\n"
  "> -\t\t\treg = <0x01f01c00 0x300>;\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tr_uart: serial at 01f02800 {\n"
+ "> -\t\tr_uart: serial@01f02800 {\n"
  "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> -\t\t\treg = <0x01f02800 0x400>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -589,7 +600,7 @@
  "> -\t\t\tstatus = \"disabled\";\n"
  "> -\t\t};\n"
  "> -\n"
- "> -\t\tr_pio: pinctrl at 01f02c00 {\n"
+ "> -\t\tr_pio: pinctrl@01f02c00 {\n"
  "> -\t\t\tcompatible = \"allwinner,sun8i-a23-r-pinctrl\";\n"
  "> -\t\t\treg = <0x01f02c00 0x400>;\n"
  "> -\t\t\tinterrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -601,7 +612,7 @@
  "> -\t\t\t#size-cells = <0>;\n"
  "> -\t\t\t#gpio-cells = <3>;\n"
  "> -\n"
- "> -\t\t\tr_uart_pins_a: r_uart at 0 {\n"
+ "> -\t\t\tr_uart_pins_a: r_uart@0 {\n"
  "> -\t\t\t\tallwinner,pins = \"PL2\", \"PL3\";\n"
  "> -\t\t\t\tallwinner,function = \"s_uart\";\n"
  "> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n"
@@ -675,7 +686,7 @@
  "> +\t\t#size-cells = <1>;\n"
  "> +\t\tranges;\n"
  "> +\n"
- "> +\t\tframebuffer at 0 {\n"
+ "> +\t\tframebuffer@0 {\n"
  "> +\t\t\tcompatible = \"allwinner,simple-framebuffer\",\n"
  "> +\t\t\t\t     \"simple-framebuffer\";\n"
  "> +\t\t\tallwinner,pipeline = \"de_be0-lcd0\";\n"
@@ -713,7 +724,7 @@
  "> +\t\t\tclock-output-names = \"osc32k\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tpll1: clk at 01c20000 {\n"
+ "> +\t\tpll1: clk@01c20000 {\n"
  "> +\t\t\t#clock-cells = <0>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n"
  "> +\t\t\treg = <0x01c20000 0x4>;\n"
@@ -721,7 +732,7 @@
  "> +\t\t\tclock-output-names = \"pll1\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tpll6: clk at 01c20028 {\n"
+ "> +\t\tpll6: clk@01c20028 {\n"
  "> +\t\t\t#clock-cells = <1>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n"
  "> +\t\t\treg = <0x01c20028 0x4>;\n"
@@ -729,7 +740,7 @@
  "> +\t\t\tclock-output-names = \"pll6\", \"pll6x2\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tcpu: cpu_clk at 01c20050 {\n"
+ "> +\t\tcpu: cpu_clk@01c20050 {\n"
  "> +\t\t\t#clock-cells = <0>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n"
  "> +\t\t\treg = <0x01c20050 0x4>;\n"
@@ -745,7 +756,7 @@
  "> +\t\t};\n"
  "> +\n"
  "> +\n"
- "> +\t\tahb1: ahb1_clk at 01c20054 {\n"
+ "> +\t\tahb1: ahb1_clk@01c20054 {\n"
  "> +\t\t\t#clock-cells = <0>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n"
  "> +\t\t\treg = <0x01c20054 0x4>;\n"
@@ -753,7 +764,7 @@
  "> +\t\t\tclock-output-names = \"ahb1\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tapb1: apb1_clk at 01c20054 {\n"
+ "> +\t\tapb1: apb1_clk@01c20054 {\n"
  "> +\t\t\t#clock-cells = <0>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n"
  "> +\t\t\treg = <0x01c20054 0x4>;\n"
@@ -761,7 +772,7 @@
  "> +\t\t\tclock-output-names = \"apb1\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tmmc0_clk: clk at 01c20088 {\n"
+ "> +\t\tmmc0_clk: clk@01c20088 {\n"
  "> +\t\t\t#clock-cells = <1>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n"
  "> +\t\t\treg = <0x01c20088 0x4>;\n"
@@ -771,7 +782,7 @@
  "> +\t\t\t\t\t     \"mmc0_sample\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tmmc1_clk: clk at 01c2008c {\n"
+ "> +\t\tmmc1_clk: clk@01c2008c {\n"
  "> +\t\t\t#clock-cells = <1>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n"
  "> +\t\t\treg = <0x01c2008c 0x4>;\n"
@@ -781,7 +792,7 @@
  "> +\t\t\t\t\t     \"mmc1_sample\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tmmc2_clk: clk at 01c20090 {\n"
+ "> +\t\tmmc2_clk: clk@01c20090 {\n"
  "> +\t\t\t#clock-cells = <1>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n"
  "> +\t\t\treg = <0x01c20090 0x4>;\n"
@@ -793,14 +804,14 @@
  "> +\n"
  "> +\t};\n"
  "> +\n"
- "> +\tsoc at 01c00000 {\n"
+ "> +\tsoc@01c00000 {\n"
  "> +\t\tcompatible = \"simple-bus\";\n"
  "> +\t\t#address-cells = <1>;\n"
  "> +\t\t#size-cells = <1>;\n"
  "> +\t\tranges;\n"
  "> +\n"
  "> +\n"
- "> +\t\tmmc0: mmc at 01c0f000 {\n"
+ "> +\t\tmmc0: mmc@01c0f000 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n"
  "> +\t\t\treg = <0x01c0f000 0x1000>;\n"
  "> +\t\t\tclocks = <&ahb1_gates 8>,\n"
@@ -819,7 +830,7 @@
  "> +\t\t\t#size-cells = <0>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tmmc1: mmc at 01c10000 {\n"
+ "> +\t\tmmc1: mmc@01c10000 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n"
  "> +\t\t\treg = <0x01c10000 0x1000>;\n"
  "> +\t\t\tclocks = <&ahb1_gates 9>,\n"
@@ -838,7 +849,7 @@
  "> +\t\t\t#size-cells = <0>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tmmc2: mmc at 01c11000 {\n"
+ "> +\t\tmmc2: mmc@01c11000 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n"
  "> +\t\t\treg = <0x01c11000 0x1000>;\n"
  "> +\t\t\tclocks = <&ahb1_gates 10>,\n"
@@ -857,7 +868,7 @@
  "> +\t\t\t#size-cells = <0>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tpio: pinctrl at 01c20800 {\n"
+ "> +\t\tpio: pinctrl@01c20800 {\n"
  "> +\t\t\treg = <0x01c20800 0x400>;\n"
  "> +\t\t\tclocks = <&apb1_gates 5>;\n"
  "> +\t\t\tgpio-controller;\n"
@@ -866,14 +877,14 @@
  "> +\t\t\t#size-cells = <0>;\n"
  "> +\t\t\t#gpio-cells = <3>;\n"
  "> +\n"
- "> +\t\t\tmmc0_pins_a: mmc0 at 0 {\n"
+ "> +\t\t\tmmc0_pins_a: mmc0@0 {\n"
  "> +\t\t\t\tallwinner,pins = \"PF0\",\"PF1\",\"PF2\",\"PF3\",\"PF4\",\"PF5\";\n"
  "> +\t\t\t\tallwinner,function = \"mmc0\";\n"
  "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n"
  "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tmmc1_pins_a: mmc1 at 0 {\n"
+ "> +\t\t\tmmc1_pins_a: mmc1@0 {\n"
  "> +\t\t\t\tallwinner,pins = \"PG0\",\"PG1\",\"PG2\",\"PG3\",\"PG4\",\"PG5\";\n"
  "> +\t\t\t\tallwinner,function = \"mmc1\";\n"
  "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n"
@@ -881,25 +892,25 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tahb1_rst: reset at 01c202c0 {\n"
+ "> +\t\tahb1_rst: reset@01c202c0 {\n"
  "> +\t\t\t#reset-cells = <1>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n"
  "> +\t\t\treg = <0x01c202c0 0xc>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tapb1_rst: reset at 01c202d0 {\n"
+ "> +\t\tapb1_rst: reset@01c202d0 {\n"
  "> +\t\t\t#reset-cells = <1>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n"
  "> +\t\t\treg = <0x01c202d0 0x4>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tapb2_rst: reset at 01c202d8 {\n"
+ "> +\t\tapb2_rst: reset@01c202d8 {\n"
  "> +\t\t\t#reset-cells = <1>;\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n"
  "> +\t\t\treg = <0x01c202d8 0x4>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\ttimer at 01c20c00 {\n"
+ "> +\t\ttimer@01c20c00 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun4i-a10-timer\";\n"
  "> +\t\t\treg = <0x01c20c00 0xa0>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,\n"
@@ -907,13 +918,13 @@
  "> +\t\t\tclocks = <&osc24M>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\twdt0: watchdog at 01c20ca0 {\n"
+ "> +\t\twdt0: watchdog@01c20ca0 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-wdt\";\n"
  "> +\t\t\treg = <0x01c20ca0 0x20>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tuart0: serial at 01c28000 {\n"
+ "> +\t\tuart0: serial@01c28000 {\n"
  "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> +\t\t\treg = <0x01c28000 0x400>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -926,7 +937,7 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tuart1: serial at 01c28400 {\n"
+ "> +\t\tuart1: serial@01c28400 {\n"
  "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> +\t\t\treg = <0x01c28400 0x400>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -939,7 +950,7 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tuart2: serial at 01c28800 {\n"
+ "> +\t\tuart2: serial@01c28800 {\n"
  "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> +\t\t\treg = <0x01c28800 0x400>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -952,7 +963,7 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tuart3: serial at 01c28c00 {\n"
+ "> +\t\tuart3: serial@01c28c00 {\n"
  "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> +\t\t\treg = <0x01c28c00 0x400>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -965,7 +976,7 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\ti2c0: i2c at 01c2ac00 {\n"
+ "> +\t\ti2c0: i2c@01c2ac00 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n"
  "> +\t\t\treg = <0x01c2ac00 0x400>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -976,7 +987,7 @@
  "> +\t\t\t#size-cells = <0>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\ti2c1: i2c at 01c2b000 {\n"
+ "> +\t\ti2c1: i2c@01c2b000 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n"
  "> +\t\t\treg = <0x01c2b000 0x400>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -987,7 +998,7 @@
  "> +\t\t\t#size-cells = <0>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\ti2c2: i2c at 01c2b400 {\n"
+ "> +\t\ti2c2: i2c@01c2b400 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n"
  "> +\t\t\treg = <0x01c2b400 0x400>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -998,7 +1009,7 @@
  "> +\t\t\t#size-cells = <0>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tgic: interrupt-controller at 01c81000 {\n"
+ "> +\t\tgic: interrupt-controller@01c81000 {\n"
  "> +\t\t\tcompatible = \"arm,cortex-a7-gic\", \"arm,cortex-a15-gic\";\n"
  "> +\t\t\treg = <0x01c81000 0x1000>,\n"
  "> +\t\t\t      <0x01c82000 0x1000>,\n"
@@ -1009,14 +1020,14 @@
  "> +\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\trtc: rtc at 01f00000 {\n"
+ "> +\t\trtc: rtc@01f00000 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun6i-a31-rtc\";\n"
  "> +\t\t\treg = <0x01f00000 0x54>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,\n"
  "> +\t\t\t\t     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tprcm at 01f01400 {\n"
+ "> +\t\tprcm@01f01400 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun8i-a23-prcm\";\n"
  "> +\t\t\treg = <0x01f01400 0x200>;\n"
  "> +\n"
@@ -1060,12 +1071,12 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tcpucfg at 01f01c00 {\n"
+ "> +\t\tcpucfg@01f01c00 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun8i-a23-cpuconfig\";\n"
  "> +\t\t\treg = <0x01f01c00 0x300>;\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tr_uart: serial at 01f02800 {\n"
+ "> +\t\tr_uart: serial@01f02800 {\n"
  "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n"
  "> +\t\t\treg = <0x01f02800 0x400>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -1076,7 +1087,7 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\tr_pio: pinctrl at 01f02c00 {\n"
+ "> +\t\tr_pio: pinctrl@01f02c00 {\n"
  "> +\t\t\tcompatible = \"allwinner,sun8i-a23-r-pinctrl\";\n"
  "> +\t\t\treg = <0x01f02c00 0x400>;\n"
  "> +\t\t\tinterrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -1088,7 +1099,7 @@
  "> +\t\t\t#size-cells = <0>;\n"
  "> +\t\t\t#gpio-cells = <3>;\n"
  "> +\n"
- "> +\t\t\tr_uart_pins_a: r_uart at 0 {\n"
+ "> +\t\t\tr_uart_pins_a: r_uart@0 {\n"
  "> +\t\t\t\tallwinner,pins = \"PL2\", \"PL3\";\n"
  "> +\t\t\t\tallwinner,function = \"s_uart\";\n"
  "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n"
@@ -1099,4 +1110,4 @@
  "> +};\n"
  >
 
-1559f4216d6c7006066f02d496048990865e2941500a216d70ad60a4d50be5cd
+d86eb8fa9ddbed455822c6b9a36f98fd2ee67901369fefb63768f133203b9143

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