diff for duplicates of <554F1C95.6060900@redhat.com> diff --git a/a/1.txt b/N1/1.txt index c7337bb..6566b88 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -5,7 +5,7 @@ On 10-05-15 08:46, Vishnu Patekar wrote: > sun8i-a23.dtsi and sun8i-a33.dtsi are same, A33 specific features > e.g. clocks can be added in future. > -> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com> +> Signed-off-by: VishnuPatekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> This seems to only contain stuff which can be shared with the a23 dts, why is this not all in the common sun8i.dtsi ? @@ -28,7 +28,7 @@ Hans > +/* > + * Copyright 2014 Chen-Yu Tsai > + * -> + * Chen-Yu Tsai <wens@csie.org> +> + * Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual @@ -78,25 +78,25 @@ Hans > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0>; > + }; > + -> + cpu at 1 { +> + cpu@1 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <1>; > + }; > + -> + cpu at 2 { +> + cpu@2 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <2>; > + }; > + -> + cpu at 3 { +> + cpu@3 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <3>; @@ -116,7 +116,7 @@ Hans > + clock-output-names = "pll5"; > + }; > + -> + axi: axi_clk at 01c20050 { +> + axi: axi_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-axi-clk"; > + reg = <0x01c20050 0x4>; @@ -124,7 +124,7 @@ Hans > + clock-output-names = "axi"; > + }; > + -> + ahb1_gates: clk at 01c20060 { +> + ahb1_gates: clk@01c20060 { > + #clock-cells = <1>; > + compatible = "allwinner,sun8i-a23-ahb1-gates-clk"; > + reg = <0x01c20060 0x8>; @@ -140,7 +140,7 @@ Hans > + "ahb1_drc"; > + }; > + -> + apb1_gates: clk at 01c20068 { +> + apb1_gates: clk@01c20068 { > + #clock-cells = <1>; > + compatible = "allwinner,sun8i-a23-apb1-gates-clk"; > + reg = <0x01c20068 0x4>; @@ -149,7 +149,7 @@ Hans > + "apb1_daudio0", "apb1_daudio1"; > + }; > + -> + apb2: clk at 01c20058 { +> + apb2: clk@01c20058 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb1-clk"; > + reg = <0x01c20058 0x4>; @@ -157,7 +157,7 @@ Hans > + clock-output-names = "apb2"; > + }; > + -> + apb2_gates: clk at 01c2006c { +> + apb2_gates: clk@01c2006c { > + #clock-cells = <1>; > + compatible = "allwinner,sun8i-a23-apb2-gates-clk"; > + reg = <0x01c2006c 0x4>; @@ -168,7 +168,7 @@ Hans > + "apb2_uart3", "apb2_uart4"; > + }; > + -> + mbus_clk: clk at 01c2015c { +> + mbus_clk: clk@01c2015c { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-mbus-clk"; > + reg = <0x01c2015c 0x4>; @@ -177,8 +177,8 @@ Hans > + }; > + }; > + -> + soc at 01c00000 { -> + dma: dma-controller at 01c02000 { +> + soc@01c00000 { +> + dma: dma-controller@01c02000 { > + compatible = "allwinner,sun8i-a23-dma"; > + reg = <0x01c02000 0x1000>; > + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; @@ -187,33 +187,33 @@ Hans > + #dma-cells = <1>; > + }; > + -> + pio: pinctrl at 01c20800 { +> + pio: pinctrl@01c20800 { > + compatible = "allwinner,sun8i-a33-pinctrl"; > + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > + -> + uart0_pins_a: uart0 at 0 { +> + uart0_pins_a: uart0@0 { > + allwinner,pins = "PF2", "PF4"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + i2c0_pins_a: i2c0 at 0 { +> + i2c0_pins_a: i2c0@0 { > + allwinner,pins = "PH2", "PH3"; > + allwinner,function = "i2c0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + i2c1_pins_a: i2c1 at 0 { +> + i2c1_pins_a: i2c1@0 { > + allwinner,pins = "PH4", "PH5"; > + allwinner,function = "i2c1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + i2c2_pins_a: i2c2 at 0 { +> + i2c2_pins_a: i2c2@0 { > + allwinner,pins = "PE12", "PE13"; > + allwinner,function = "i2c2"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; @@ -221,14 +221,14 @@ Hans > + }; > + }; > + -> + lradc: lradc at 01c22800 { +> + lradc: lradc@01c22800 { > + compatible = "allwinner,sun4i-a10-lradc-keys"; > + reg = <0x01c22800 0x100>; > + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + -> + uart4: serial at 01c29000 { +> + uart4: serial@01c29000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c29000 0x400>; > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; diff --git a/a/content_digest b/N1/content_digest index 515f887..816efad 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,21 @@ "ref\01431240383-12763-1-git-send-email-vishnupatekar0510@gmail.com\0" "ref\01431240383-12763-6-git-send-email-vishnupatekar0510@gmail.com\0" - "From\0hdegoede@redhat.com (Hans de Goede)\0" - "Subject\0[PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI\0" + "ref\01431240383-12763-6-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" + "From\0Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>\0" + "Subject\0Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI\0" "Date\0Sun, 10 May 2015 10:53:41 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>" + maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org + emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org + linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + " robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org\0" + "Cc\0wens-jdAy2FN1RRM@public.gmane.org" + jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org + arnd-r2nGTMty4D4@public.gmane.org + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org + " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" "\00:1\0" "b\0" "Hi,\n" @@ -13,7 +25,7 @@ "> sun8i-a23.dtsi and sun8i-a33.dtsi are same, A33 specific features\n" "> e.g. clocks can be added in future.\n" ">\n" - "> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>\n" + "> Signed-off-by: VishnuPatekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" "\n" "This seems to only contain stuff which can be shared with the a23 dts,\n" "why is this not all in the common sun8i.dtsi ?\n" @@ -36,7 +48,7 @@ "> +/*\n" "> + * Copyright 2014 Chen-Yu Tsai\n" "> + *\n" - "> + * Chen-Yu Tsai <wens@csie.org>\n" + "> + * Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>\n" "> + *\n" "> + * This file is dual-licensed: you can use it either under the terms\n" "> + * of the GPL or the X11 license, at your option. Note that this dual\n" @@ -86,25 +98,25 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <3>;\n" @@ -124,7 +136,7 @@ "> +\t\t\tclock-output-names = \"pll5\";\n" "> +\t\t};\n" "> +\n" - "> +\t\taxi: axi_clk at 01c20050 {\n" + "> +\t\taxi: axi_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-axi-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -132,7 +144,7 @@ "> +\t\t\tclock-output-names = \"axi\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb1_gates: clk at 01c20060 {\n" + "> +\t\tahb1_gates: clk@01c20060 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-ahb1-gates-clk\";\n" "> +\t\t\treg = <0x01c20060 0x8>;\n" @@ -148,7 +160,7 @@ "> +\t\t\t\t\t\"ahb1_drc\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb1_gates: clk at 01c20068 {\n" + "> +\t\tapb1_gates: clk@01c20068 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-apb1-gates-clk\";\n" "> +\t\t\treg = <0x01c20068 0x4>;\n" @@ -157,7 +169,7 @@ "> +\t\t\t\t\t\"apb1_daudio0\",\t\"apb1_daudio1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb2: clk at 01c20058 {\n" + "> +\t\tapb2: clk@01c20058 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n" "> +\t\t\treg = <0x01c20058 0x4>;\n" @@ -165,7 +177,7 @@ "> +\t\t\tclock-output-names = \"apb2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb2_gates: clk at 01c2006c {\n" + "> +\t\tapb2_gates: clk@01c2006c {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-apb2-gates-clk\";\n" "> +\t\t\treg = <0x01c2006c 0x4>;\n" @@ -176,7 +188,7 @@ "> +\t\t\t\t\t\"apb2_uart3\", \"apb2_uart4\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmbus_clk: clk at 01c2015c {\n" + "> +\t\tmbus_clk: clk@01c2015c {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-mbus-clk\";\n" "> +\t\t\treg = <0x01c2015c 0x4>;\n" @@ -185,8 +197,8 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tsoc at 01c00000 {\n" - "> +\t\tdma: dma-controller at 01c02000 {\n" + "> +\tsoc@01c00000 {\n" + "> +\t\tdma: dma-controller@01c02000 {\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-dma\";\n" "> +\t\t\treg = <0x01c02000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -195,33 +207,33 @@ "> +\t\t\t#dma-cells = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tpio: pinctrl at 01c20800 {\n" + "> +\t\tpio: pinctrl@01c20800 {\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a33-pinctrl\";\n" "> +\t\t\tinterrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,\n" "> +\t\t\t\t <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\n" - "> +\t\t\tuart0_pins_a: uart0 at 0 {\n" + "> +\t\t\tuart0_pins_a: uart0@0 {\n" "> +\t\t\t\tallwinner,pins = \"PF2\", \"PF4\";\n" "> +\t\t\t\tallwinner,function = \"uart0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ti2c0_pins_a: i2c0 at 0 {\n" + "> +\t\t\ti2c0_pins_a: i2c0@0 {\n" "> +\t\t\t\tallwinner,pins = \"PH2\", \"PH3\";\n" "> +\t\t\t\tallwinner,function = \"i2c0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ti2c1_pins_a: i2c1 at 0 {\n" + "> +\t\t\ti2c1_pins_a: i2c1@0 {\n" "> +\t\t\t\tallwinner,pins = \"PH4\", \"PH5\";\n" "> +\t\t\t\tallwinner,function = \"i2c1\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ti2c2_pins_a: i2c2 at 0 {\n" + "> +\t\t\ti2c2_pins_a: i2c2@0 {\n" "> +\t\t\t\tallwinner,pins = \"PE12\", \"PE13\";\n" "> +\t\t\t\tallwinner,function = \"i2c2\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" @@ -229,14 +241,14 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tlradc: lradc at 01c22800 {\n" + "> +\t\tlradc: lradc@01c22800 {\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-lradc-keys\";\n" "> +\t\t\treg = <0x01c22800 0x100>;\n" "> +\t\t\tinterrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart4: serial at 01c29000 {\n" + "> +\t\tuart4: serial@01c29000 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c29000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -252,4 +264,4 @@ "> +};\n" > -652c9a23fcd82d5589732c7f2ec4da28b9f69c9ce18fdcf7b1674e676cc9c315 +d2218bf0f23db99ffa5127e901258ea0147831043d5c1a091bcdc0ae9da13e92
diff --git a/a/1.txt b/N2/1.txt index c7337bb..fe65590 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -78,25 +78,25 @@ Hans > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0>; > + }; > + -> + cpu at 1 { +> + cpu@1 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <1>; > + }; > + -> + cpu at 2 { +> + cpu@2 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <2>; > + }; > + -> + cpu at 3 { +> + cpu@3 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <3>; @@ -116,7 +116,7 @@ Hans > + clock-output-names = "pll5"; > + }; > + -> + axi: axi_clk at 01c20050 { +> + axi: axi_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-axi-clk"; > + reg = <0x01c20050 0x4>; @@ -124,7 +124,7 @@ Hans > + clock-output-names = "axi"; > + }; > + -> + ahb1_gates: clk at 01c20060 { +> + ahb1_gates: clk@01c20060 { > + #clock-cells = <1>; > + compatible = "allwinner,sun8i-a23-ahb1-gates-clk"; > + reg = <0x01c20060 0x8>; @@ -140,7 +140,7 @@ Hans > + "ahb1_drc"; > + }; > + -> + apb1_gates: clk at 01c20068 { +> + apb1_gates: clk@01c20068 { > + #clock-cells = <1>; > + compatible = "allwinner,sun8i-a23-apb1-gates-clk"; > + reg = <0x01c20068 0x4>; @@ -149,7 +149,7 @@ Hans > + "apb1_daudio0", "apb1_daudio1"; > + }; > + -> + apb2: clk at 01c20058 { +> + apb2: clk@01c20058 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb1-clk"; > + reg = <0x01c20058 0x4>; @@ -157,7 +157,7 @@ Hans > + clock-output-names = "apb2"; > + }; > + -> + apb2_gates: clk at 01c2006c { +> + apb2_gates: clk@01c2006c { > + #clock-cells = <1>; > + compatible = "allwinner,sun8i-a23-apb2-gates-clk"; > + reg = <0x01c2006c 0x4>; @@ -168,7 +168,7 @@ Hans > + "apb2_uart3", "apb2_uart4"; > + }; > + -> + mbus_clk: clk at 01c2015c { +> + mbus_clk: clk@01c2015c { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-mbus-clk"; > + reg = <0x01c2015c 0x4>; @@ -177,8 +177,8 @@ Hans > + }; > + }; > + -> + soc at 01c00000 { -> + dma: dma-controller at 01c02000 { +> + soc@01c00000 { +> + dma: dma-controller@01c02000 { > + compatible = "allwinner,sun8i-a23-dma"; > + reg = <0x01c02000 0x1000>; > + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; @@ -187,33 +187,33 @@ Hans > + #dma-cells = <1>; > + }; > + -> + pio: pinctrl at 01c20800 { +> + pio: pinctrl@01c20800 { > + compatible = "allwinner,sun8i-a33-pinctrl"; > + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > + -> + uart0_pins_a: uart0 at 0 { +> + uart0_pins_a: uart0@0 { > + allwinner,pins = "PF2", "PF4"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + i2c0_pins_a: i2c0 at 0 { +> + i2c0_pins_a: i2c0@0 { > + allwinner,pins = "PH2", "PH3"; > + allwinner,function = "i2c0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + i2c1_pins_a: i2c1 at 0 { +> + i2c1_pins_a: i2c1@0 { > + allwinner,pins = "PH4", "PH5"; > + allwinner,function = "i2c1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + i2c2_pins_a: i2c2 at 0 { +> + i2c2_pins_a: i2c2@0 { > + allwinner,pins = "PE12", "PE13"; > + allwinner,function = "i2c2"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; @@ -221,14 +221,14 @@ Hans > + }; > + }; > + -> + lradc: lradc at 01c22800 { +> + lradc: lradc@01c22800 { > + compatible = "allwinner,sun4i-a10-lradc-keys"; > + reg = <0x01c22800 0x100>; > + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + -> + uart4: serial at 01c29000 { +> + uart4: serial@01c29000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c29000 0x400>; > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; diff --git a/a/content_digest b/N2/content_digest index 515f887..3a44b94 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,9 +1,20 @@ "ref\01431240383-12763-1-git-send-email-vishnupatekar0510@gmail.com\0" "ref\01431240383-12763-6-git-send-email-vishnupatekar0510@gmail.com\0" - "From\0hdegoede@redhat.com (Hans de Goede)\0" - "Subject\0[PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI\0" + "From\0Hans de Goede <hdegoede@redhat.com>\0" + "Subject\0Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI\0" "Date\0Sun, 10 May 2015 10:53:41 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Vishnu Patekar <vishnupatekar0510@gmail.com>" + maxime.ripard@free-electrons.com + emilio@elopez.com.ar + linus.walleij@linaro.org + " robh+dt@kernel.org\0" + "Cc\0wens@csie.org" + jenskuske@gmail.com + arnd@arndb.de + linux-arm-kernel@lists.infradead.org + linux-kernel@vger.kernel.org + linux-sunxi@googlegroups.com + " devicetree@vger.kernel.org\0" "\00:1\0" "b\0" "Hi,\n" @@ -86,25 +97,25 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <3>;\n" @@ -124,7 +135,7 @@ "> +\t\t\tclock-output-names = \"pll5\";\n" "> +\t\t};\n" "> +\n" - "> +\t\taxi: axi_clk at 01c20050 {\n" + "> +\t\taxi: axi_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-axi-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -132,7 +143,7 @@ "> +\t\t\tclock-output-names = \"axi\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb1_gates: clk at 01c20060 {\n" + "> +\t\tahb1_gates: clk@01c20060 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-ahb1-gates-clk\";\n" "> +\t\t\treg = <0x01c20060 0x8>;\n" @@ -148,7 +159,7 @@ "> +\t\t\t\t\t\"ahb1_drc\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb1_gates: clk at 01c20068 {\n" + "> +\t\tapb1_gates: clk@01c20068 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-apb1-gates-clk\";\n" "> +\t\t\treg = <0x01c20068 0x4>;\n" @@ -157,7 +168,7 @@ "> +\t\t\t\t\t\"apb1_daudio0\",\t\"apb1_daudio1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb2: clk at 01c20058 {\n" + "> +\t\tapb2: clk@01c20058 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n" "> +\t\t\treg = <0x01c20058 0x4>;\n" @@ -165,7 +176,7 @@ "> +\t\t\tclock-output-names = \"apb2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb2_gates: clk at 01c2006c {\n" + "> +\t\tapb2_gates: clk@01c2006c {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-apb2-gates-clk\";\n" "> +\t\t\treg = <0x01c2006c 0x4>;\n" @@ -176,7 +187,7 @@ "> +\t\t\t\t\t\"apb2_uart3\", \"apb2_uart4\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmbus_clk: clk at 01c2015c {\n" + "> +\t\tmbus_clk: clk@01c2015c {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-mbus-clk\";\n" "> +\t\t\treg = <0x01c2015c 0x4>;\n" @@ -185,8 +196,8 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tsoc at 01c00000 {\n" - "> +\t\tdma: dma-controller at 01c02000 {\n" + "> +\tsoc@01c00000 {\n" + "> +\t\tdma: dma-controller@01c02000 {\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-dma\";\n" "> +\t\t\treg = <0x01c02000 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -195,33 +206,33 @@ "> +\t\t\t#dma-cells = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tpio: pinctrl at 01c20800 {\n" + "> +\t\tpio: pinctrl@01c20800 {\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a33-pinctrl\";\n" "> +\t\t\tinterrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,\n" "> +\t\t\t\t <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\n" - "> +\t\t\tuart0_pins_a: uart0 at 0 {\n" + "> +\t\t\tuart0_pins_a: uart0@0 {\n" "> +\t\t\t\tallwinner,pins = \"PF2\", \"PF4\";\n" "> +\t\t\t\tallwinner,function = \"uart0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ti2c0_pins_a: i2c0 at 0 {\n" + "> +\t\t\ti2c0_pins_a: i2c0@0 {\n" "> +\t\t\t\tallwinner,pins = \"PH2\", \"PH3\";\n" "> +\t\t\t\tallwinner,function = \"i2c0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ti2c1_pins_a: i2c1 at 0 {\n" + "> +\t\t\ti2c1_pins_a: i2c1@0 {\n" "> +\t\t\t\tallwinner,pins = \"PH4\", \"PH5\";\n" "> +\t\t\t\tallwinner,function = \"i2c1\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ti2c2_pins_a: i2c2 at 0 {\n" + "> +\t\t\ti2c2_pins_a: i2c2@0 {\n" "> +\t\t\t\tallwinner,pins = \"PE12\", \"PE13\";\n" "> +\t\t\t\tallwinner,function = \"i2c2\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" @@ -229,14 +240,14 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tlradc: lradc at 01c22800 {\n" + "> +\t\tlradc: lradc@01c22800 {\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-lradc-keys\";\n" "> +\t\t\treg = <0x01c22800 0x100>;\n" "> +\t\t\tinterrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart4: serial at 01c29000 {\n" + "> +\t\tuart4: serial@01c29000 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c29000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -252,4 +263,4 @@ "> +};\n" > -652c9a23fcd82d5589732c7f2ec4da28b9f69c9ce18fdcf7b1674e676cc9c315 +d5f71f8ed86400994fcfc41b3785945f8409019ebdc19cb006151746ad059db2
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