From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59813) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yru9V-0006da-CX for qemu-devel@nongnu.org; Mon, 11 May 2015 16:18:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yru9Q-0000Bc-72 for qemu-devel@nongnu.org; Mon, 11 May 2015 16:18:13 -0400 Received: from mail-qc0-x233.google.com ([2607:f8b0:400d:c01::233]:36373) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yru9Q-0000BR-1n for qemu-devel@nongnu.org; Mon, 11 May 2015 16:18:08 -0400 Received: by qcbgy10 with SMTP id gy10so75158260qcb.3 for ; Mon, 11 May 2015 13:18:07 -0700 (PDT) Sender: Richard Henderson Message-ID: <55510E7B.4050209@twiddle.net> Date: Mon, 11 May 2015 13:18:03 -0700 From: Richard Henderson MIME-Version: 1.0 References: <6920fa40d097d15d0cfcaf63c26b6325ee5edc46.1431322749.git.crosthwaite.peter@gmail.com> <55508206.5040206@suse.de> <55508368.3010300@redhat.com> In-Reply-To: <55508368.3010300@redhat.com> Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [RFC PATCH 02/34] tcg+qom: QOMify core CPU defintions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , =?ISO-8859-15?Q?Andreas_F=E4rb?= =?ISO-8859-15?Q?er?= , Peter Crosthwaite , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, edgari@xilinx.com, sorenb@xilinx.com On 05/11/2015 03:24 AM, Paolo Bonzini wrote: > > > On 11/05/2015 12:18, Andreas Färber wrote: >>>> + int (*cpu_mmu_index)(CPUState *cpu); >>>> + void (*cpu_get_tb_cpu_state)(CPUState *cpu, >>>> + void *pc, /* target_long * */ >>>> + void *cs_base, /* target_long */ >>>> + int *flags); >>>> + void (*gen_intermediate_code)(void *env, struct TranslationBlock *tb); >>>> + void (*gen_intermediate_code_pc)(void *env, struct TranslationBlock *tb); >>>> + void (*restore_state_to_opc)(void *env, struct TranslationBlock *tb, >>>> + int pc_pos); >>>> + void (*tlb_fill)(CPUState *cs, uint64_t addr, int is_write, int mmu_idx, >>>> + uintptr_t retaddr); >>>> } CPUClass; >>>> >>>> #ifdef HOST_WORDS_BIGENDIAN >> [snip] >> >> Paolo had objected to this when I tried it. The counter-suggestion was >> something about reworking how the cputlb code is built per target - >> please check the archives. > > Right. My point was that these functions are not polymorphic. Each > call to these should know exactly which function to call. That's some major surgery you have planned there. Especially the path via the qemu_ld/st helpers, where function to call is currently hard-coded into the tcg backend. I think that this is a decent step forward, modulo the conditionals along the use paths. I think we ought to clean up all of the translators to the new QOM hooks. I can't imagine that most of these hooks are called frequently enough that the indirect call really matters. Certainly gen_intermediate_code need not use the hook when initializing the mmu_idx in the DisasContext. That said, I'd approve of a goal to arrange for the correct qemu_ld/st helpers to be called, and a direct call to the proper tlb_fill. But, one step at a time... r~