From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44008) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ys6ln-0001nR-2H for qemu-devel@nongnu.org; Tue, 12 May 2015 05:46:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ys6lj-0007fC-27 for qemu-devel@nongnu.org; Tue, 12 May 2015 05:46:35 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:3312) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ys6li-0007eo-SZ for qemu-devel@nongnu.org; Tue, 12 May 2015 05:46:30 -0400 Message-ID: <5551CB3A.3020300@imgtec.com> Date: Tue, 12 May 2015 10:43:22 +0100 From: Leon Alrae MIME-Version: 1.0 References: <1431343850-46198-1-git-send-email-yongbok.kim@imgtec.com> <1431343850-46198-3-git-send-email-yongbok.kim@imgtec.com> In-Reply-To: <1431343850-46198-3-git-send-email-yongbok.kim@imgtec.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2 2/2] target-mips: Misaligned memory accesses for MSA List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yongbok Kim , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org On 11/05/2015 12:30, Yongbok Kim wrote: > @@ -391,6 +391,37 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *en= v, target_ulong address, int r > } > } > =20 > +bool cpu_mips_validate_msa_block_access(CPUMIPSState *env, target_ulon= g addr, > + int rw, int mmu_idx) > +{ > + target_ulong vaddr =3D addr & TARGET_PAGE_MASK; This deserves more descriptive name, maybe "page_addr"? > + target_ulong badvaddr =3D addr; > + > + CPUState *cs =3D CPU(mips_env_get_cpu(env)); > + int ret; > + > + ret =3D mips_cpu_handle_mmu_fault(cs, vaddr, rw, mmu_idx); > + if (ret !=3D TLBRET_MATCH) { > + /* calling raise_mmu_exeception again to correct badvaddr */ > + raise_mmu_exception(env, badvaddr, rw, ret); mips_cpu_handle_mmu_fault() already calls raise_mmu_exception() where appropriate registers get updated. Why calling it again here? > + return false; > + } > + if (unlikely(((addr & ~TARGET_PAGE_MASK) + MSA_WRLEN - 1) > + >=3D TARGET_PAGE_SIZE)) { This isn=92t required, you already do this before calling this function. > + vaddr +=3D TARGET_PAGE_SIZE; > + ret =3D mips_cpu_handle_mmu_fault(cs, vaddr, rw, mmu_idx); > + if (ret !=3D TLBRET_MATCH) { > + if (ret !=3D TLBRET_BADADDR) { > + badvaddr =3D vaddr; > + } > + /* calling raise_mmu_exeception again to correct badvaddr = */ > + raise_mmu_exception(env, badvaddr, rw, ret); > + return false; > + } > + } > + return true; > +} > + > static const char * const excp_names[EXCP_LAST + 1] =3D { > [EXCP_RESET] =3D "reset", > [EXCP_SRESET] =3D "soft reset", > @@ -3571,33 +3576,47 @@ void helper_msa_ld_df(CPUMIPSState *env, uint32= _t df, uint32_t wd, uint32_t rs, > wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); > target_ulong addr =3D env->active_tc.gpr[rs] + (s10 << df); > int i; > + int mmu_idx =3D cpu_mmu_index(env); > + > +#if !defined(CONFIG_USER_ONLY) > + if (unlikely(((addr & ~TARGET_PAGE_MASK) + MSA_WRLEN - 1) > + >=3D TARGET_PAGE_SIZE)) { MSA_WRLEN/8 > + if (!cpu_mips_validate_msa_block_access(env, addr, MMU_DATA_LO= AD, > + mmu_idx)) { > + CPUState *cs =3D CPU(mips_env_get_cpu(env)); > + helper_raise_exception_err(env, cs->exception_index, > + env->error_code); Wouldn=92t it be better to fold it into cpu_mips_validate_msa_block_acces= s()? Thanks, Leon