From: Jan Kiszka <jan.kiszka@siemens.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v7 07/17] ARM: Put target PC for PSCI CPU_ON on per-CPU stack
Date: Wed, 13 May 2015 09:31:22 +0200 [thread overview]
Message-ID: <5552FDCA.1060901@siemens.com> (raw)
In-Reply-To: <BN1PR03MB18872E5D8DADEBC661482009DD90@BN1PR03MB188.namprd03.prod.outlook.com>
On 2015-05-13 09:21, Wang Dongsheng wrote:
>
>
>> -----Original Message-----
>> From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Jan Kiszka
>> Sent: Tuesday, April 21, 2015 1:19 PM
>> To: U-Boot Mailing List; Tom Rini
>> Cc: Marc Zyngier; Tom Warren; Paul Walmsley; Ian Campbell; Thierry Reding
>> Subject: [U-Boot] [PATCH v7 07/17] ARM: Put target PC for PSCI CPU_ON on per-CPU
>> stack
>>
>> Use a per-CPU variable for saving the target PC during CPU_ON operations. This
>> allows us to run this service independently on targets that have more than 2
>> cores and also core-local power control.
>>
>> CC: Marc Zyngier <marc.zyngier@arm.com>
>> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
>> Reviewed-by: Tom Rini <trini@konsulko.com>
>> Reviewed-by: Thierry Reding <treding@nvidia.com>
>> Tested-by: Thierry Reding <treding@nvidia.com>
>> Tested-by: Ian Campbell <ijc@hellion.org.uk>
>> ---
>> arch/arm/cpu/armv7/psci.S | 11 +++++------
>> arch/arm/cpu/armv7/sunxi/psci.S | 9 ++++++---
>> 2 files changed, 11 insertions(+), 9 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index
>> 18d85c4..87c0c0b 100644
>> --- a/arch/arm/cpu/armv7/psci.S
>> +++ b/arch/arm/cpu/armv7/psci.S
>> @@ -17,6 +17,7 @@
>>
>> #include <config.h>
>> #include <linux/linkage.h>
>> +#include <asm/macro.h>
>> #include <asm/psci.h>
>>
>> .pushsection ._secure.text, "ax"
>> @@ -202,6 +203,7 @@ ENTRY(psci_get_cpu_stack_top)
>> add r5, r5, #0x2000 @ Skip two pages
>> lsr r5, r5, #12 @ Align to start of page
>> lsl r5, r5, #12
>> + sub r5, r5, #4 @ reserve 1 word for target PC
>> sub r0, r5, r0 @ here's our stack!
>>
>> bx lr
>> @@ -212,13 +214,10 @@ ENTRY(psci_cpu_entry)
>>
>> bl _nonsec_init
>>
>> - adr r0, _psci_target_pc
>> - ldr r0, [r0]
>> + bl psci_get_cpu_id @ CPU ID => r0
>> + bl psci_get_cpu_stack_top @ stack top => r0
>> + ldr r0, [r0] @ target PC at stack top
>> b _do_nonsec_entry
>> ENDPROC(psci_cpu_entry)
>>
>> -.globl _psci_target_pc
>> -_psci_target_pc:
>> - .word 0
>> -
>> .popsection
>> diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
>> index dd583b2..7ec0500 100644
>> --- a/arch/arm/cpu/armv7/sunxi/psci.S
>> +++ b/arch/arm/cpu/armv7/sunxi/psci.S
>> @@ -139,8 +139,11 @@ out: mcr p15, 0, r7, c1, c1, 0
>> @ r2 = target PC
>> .globl psci_cpu_on
>> psci_cpu_on:
>> - ldr r0, =_psci_target_pc
>> - str r2, [r0]
>> + push {lr}
>> +
>> + mov r0, r1
>> + bl psci_get_cpu_stack_top @ get stack top of target CPU
>> + str r2, [r0] @ store target PC at stack top
>
> Base on target PC will be saved in stack. The cpu(r1) should be mask firstly.
> Because r1 value is 0xf0x, and it is not what we expected cpu value(0x1 or ...).
> If not, the stack address is incorrect.
>
> When I develop LS1021a PSCI code, I found this issue. So I think sunxi also has this
> issue.
IIRC, sunxi has no clusters != 0 so far, but you are right conceptually.
We already mask elsewhere in that function, so the instruction should
simply be moved up here.
Jan
--
Siemens AG, Corporate Technology, CT RTC ITP SES-DE
Corporate Competence Center Embedded Linux
next prev parent reply other threads:[~2015-05-13 7:31 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-21 5:18 [U-Boot] [PATCH v7 00/17] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix Jan Kiszka
2015-04-21 5:18 ` [U-Boot] [PATCH v7 01/17] ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditions Jan Kiszka
2015-04-22 6:02 ` Huan Wang
2015-04-22 14:03 ` Andre Przywara
2015-04-22 14:31 ` Jan Kiszka
2015-04-21 5:18 ` [U-Boot] [PATCH v7 02/17] sun7i: Remove duplicate call to psci_arch_init Jan Kiszka
2015-04-21 5:18 ` [U-Boot] [PATCH v7 03/17] ARM: Factor out common psci_get_cpu_id Jan Kiszka
2015-04-21 5:18 ` [U-Boot] [PATCH v7 04/17] ARM: Factor out reusable psci_cpu_off_common Jan Kiszka
2015-04-21 5:18 ` [U-Boot] [PATCH v7 05/17] ARM: Factor out reusable psci_cpu_entry Jan Kiszka
2015-04-21 5:18 ` [U-Boot] [PATCH v7 06/17] ARM: Factor out reusable psci_get_cpu_stack_top Jan Kiszka
2015-04-21 5:18 ` [U-Boot] [PATCH v7 07/17] ARM: Put target PC for PSCI CPU_ON on per-CPU stack Jan Kiszka
2015-05-13 7:21 ` Wang Dongsheng
2015-05-13 7:31 ` Jan Kiszka [this message]
2015-05-13 8:06 ` Wang Dongsheng
2015-04-21 5:18 ` [U-Boot] [PATCH v7 08/17] tegra124: Add more registers to struct mc_ctlr Jan Kiszka
2015-04-21 5:18 ` [U-Boot] [PATCH v7 09/17] virt-dt: Allow reservation of secure region when in a RAM carveout Jan Kiszka
2015-04-21 5:18 ` [U-Boot] [PATCH v7 10/17] tegra: Make tegra_powergate_power_on public Jan Kiszka
2015-04-21 5:18 ` [U-Boot] [PATCH v7 11/17] ARM: Add board-specific initialization hook for PSCI Jan Kiszka
2015-04-21 5:18 ` [U-Boot] [PATCH v7 12/17] tegra124: Add PSCI support for Tegra124 Jan Kiszka
2015-04-21 5:18 ` [U-Boot] [PATCH v7 13/17] tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 Jan Kiszka
2015-04-21 5:18 ` [U-Boot] [PATCH v7 14/17] tegra: Set CNTFRQ for secondary CPUs Jan Kiszka
2015-04-21 5:18 ` [U-Boot] [PATCH v7 15/17] ARM: tegra: Enable SMMU when going non-secure Jan Kiszka
2015-04-21 5:18 ` [U-Boot] [PATCH v7 16/17] tegra: Boot in non-secure mode by default Jan Kiszka
2015-04-21 5:18 ` [U-Boot] [PATCH v7 17/17] jetson-tk1: Add PSCI configuration options and reserve secure code Jan Kiszka
2015-04-21 17:58 ` Ian Campbell
2015-04-21 18:10 ` Jan Kiszka
2015-04-21 15:33 ` [U-Boot] [PATCH v7 00/17] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix Stephen Warren
2015-05-08 6:01 ` Jan Kiszka
2015-05-08 15:40 ` Tom Warren
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