From: Paolo Bonzini <pbonzini@redhat.com>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Peter Crosthwaite <peter.crosthwaite@xilinx.com>,
Richard Henderson <rth@twiddle.net>,
QEMU Developers <qemu-devel@nongnu.org>,
Greg Bellows <greg.bellows@linaro.org>
Subject: Re: [Qemu-devel] Supporting multiple CPU AddressSpaces and memory transaction attributes
Date: Wed, 13 May 2015 13:36:10 +0200 [thread overview]
Message-ID: <5553372A.60409@redhat.com> (raw)
In-Reply-To: <20150513112104.GC13061@toto>
On 13/05/2015 13:21, Edgar E. Iglesias wrote:
>
> It was not clear to me if CPUs should hook into the iommu notification
> system or if we should make the iommu notification code signal changes
> through AS change notifications.
>
> The latter would be easy to get right I guess but we wouldn't be
> able to have any granularity in the flushing so performance could
> be better if the CPU somehow knows what parts have changed.
I think it's CPUs that should hook and flush their TLBs.
Paolo
prev parent reply other threads:[~2015-05-13 11:36 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-04 17:47 [Qemu-devel] Supporting multiple CPU AddressSpaces and memory transaction attributes Peter Maydell
2014-09-06 0:26 ` Peter Crosthwaite
2014-09-06 10:30 ` Peter Maydell
2014-09-07 1:47 ` Edgar E. Iglesias
2014-09-08 11:53 ` Peter Maydell
2014-09-09 1:09 ` Edgar E. Iglesias
2015-05-12 14:47 ` Peter Maydell
2015-05-13 6:41 ` Edgar E. Iglesias
2015-05-13 9:28 ` Paolo Bonzini
2015-05-13 11:21 ` Edgar E. Iglesias
2015-05-13 11:36 ` Paolo Bonzini [this message]
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