Re: IP30: SMP, Almost there?

[Joshua Kinard <kumba@gentoo.org>]

On 05/18/2015 08:01, Joshua Kinard wrote:
> On 05/18/2015 01:39, Joshua Kinard wrote:
>> So I've gotten the second CPU in Octane to "tick" again...somehow.  I am
>> certain someone's cat went missing in the process...
>>
>> Anyways, it's booting into an initramfs and dying almost immediately with
>> errors from do_page_fault:

I've stripped the kernel config down to practically nothing (9MB w/ debugging,
-Os, and a small initramfs), yet still, when CPU1 starts up and starts
scheduling, I am running into "scheduling while atomic" warnings (due to
enabling that option in kernel debugging).  CPU0 then joins in with scheduling
while atomic.  I've tried switching to mutexes instead of spinlocks, but no
dice.  It seems to be stemming from core kernel code, but I know the problem
has to be in the IP30 SMP code.

I've looked at all of the other MIPS SMP implementations, and by far the one
that looks the closest is the Sibyte 1250 SMP code.  Everything else is far too
different, what with multicores and multithreading.  However, adopting most of
the Sibyte semantics for CPU1 bringup doesn't appear to work.  Only thing I
haven't done yet is handle CPU affinity.

Do I need to define the irq_set_affinity() function pointer in struct irq_chip?
 IP27 doesn't have this and no real ill effects w/ SMP are seen on that system
(just the random hardlock due to that vmscan BUG() or disk I/O).  Am I not
masking all IRQs correctly and running into a case of recursive interrupts?  Is
there still a way to halt all interrupts globally (the old big lock) and use
that as a debugging aid?

--J