From: Richard Henderson <rth@twiddle.net>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v2 00/10] TriCore v1.6.1 ISA and missing v1.6 instructions
Date: Fri, 22 May 2015 07:50:01 -0700 [thread overview]
Message-ID: <555F4219.4020509@twiddle.net> (raw)
In-Reply-To: <1432282979-24500-1-git-send-email-kbastian@mail.uni-paderborn.de>
On 05/22/2015 01:22 AM, Bastian Koppelmann wrote:
> Hi,
>
> the new Aurix platform introduces a new ISA version, so this patchset
> adds a new feature bit and changes the generic Aurix cpu to a more specific
> tc27x cpu model. While at this, it introduces a new cpu model tc1797 which
> uses the v1.3.1 ISA and fixes the tc1796 to us the v1.3 ISA.
>
> It also adds the with v1.6.1 introduces instructions cmpswap, swapmsk and
> crc32. While at this, it adds the missing instructions of the v1.6 ISA.
>
> Cheers,
> Bastian
>
> v1->v2:
> - FRET and FCALL don't create a wrong register state anymore, if the load traps.
Reviewed-by: Richard Henderson <rth@twiddle.net>
r~
prev parent reply other threads:[~2015-05-22 14:50 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-22 8:22 [Qemu-devel] [PATCH v2 00/10] TriCore v1.6.1 ISA and missing v1.6 instructions Bastian Koppelmann
2015-05-22 8:22 ` [Qemu-devel] [PATCH v2 01/10] target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3 Bastian Koppelmann
2015-05-22 8:22 ` [Qemu-devel] [PATCH v2 02/10] target-tricore: introduce ISA v1.6.1 feature Bastian Koppelmann
2015-05-22 8:22 ` [Qemu-devel] [PATCH v2 03/10] target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA Bastian Koppelmann
2015-05-22 8:22 ` [Qemu-devel] [PATCH v2 04/10] target-tricore: add CMPSWP instructions of the v1.6.1 ISA Bastian Koppelmann
2015-05-22 8:22 ` [Qemu-devel] [PATCH v2 05/10] target-tricore: add SWAPMSK " Bastian Koppelmann
2015-05-22 8:22 ` [Qemu-devel] [PATCH v2 06/10] target-tricore: add RR_CRC32 instruction " Bastian Koppelmann
2015-05-22 8:22 ` [Qemu-devel] [PATCH v2 07/10] target-tricore: add SYS_RESTORE instruction of the v1.6 ISA Bastian Koppelmann
2015-05-22 8:22 ` [Qemu-devel] [PATCH v2 08/10] target-tricore: add FCALL instructions " Bastian Koppelmann
2015-05-22 8:22 ` [Qemu-devel] [PATCH v2 09/10] target-tricore: add FRET " Bastian Koppelmann
2015-05-22 8:22 ` [Qemu-devel] [PATCH v2 10/10] target-tricore: add RR_DIV and RR_DIV_U " Bastian Koppelmann
2015-05-22 14:50 ` Richard Henderson [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=555F4219.4020509@twiddle.net \
--to=rth@twiddle.net \
--cc=kbastian@mail.uni-paderborn.de \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.