From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 23 May 2015 02:02:55 +0200 (CEST) Received: from mailapp01.imgtec.com ([195.59.15.196]:35805 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27006688AbbEWACxdvEF7 (ORCPT ); Sat, 23 May 2015 02:02:53 +0200 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 2C85879E39888; Sat, 23 May 2015 01:02:46 +0100 (IST) Received: from hhmail02.hh.imgtec.org (10.100.10.20) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Sat, 23 May 2015 01:00:47 +0100 Received: from BAMAIL02.ba.imgtec.org (10.20.40.28) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.224.2; Sat, 23 May 2015 01:00:47 +0100 Received: from [10.20.3.79] (10.20.3.79) by bamail02.ba.imgtec.org (10.20.40.28) with Microsoft SMTP Server (TLS) id 14.3.174.1; Fri, 22 May 2015 17:00:42 -0700 Message-ID: <555FC32A.4020308@imgtec.com> Date: Fri, 22 May 2015 17:00:42 -0700 From: Leonid Yegoshin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Ralf Baechle CC: , , , , , , , , , , , , Subject: Re: [PATCH 1/2] MIPS: MSA: bugfix - disable MSA during thread switch correctly References: <20150519211222.35859.52798.stgit@ubuntu-yegoshin> <20150519211351.35859.80332.stgit@ubuntu-yegoshin> <20150522093812.GH6941@linux-mips.org> <555F776E.3070904@imgtec.com> <20150522232019.GA10556@linux-mips.org> In-Reply-To: <20150522232019.GA10556@linux-mips.org> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.20.3.79] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 47592 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Leonid.Yegoshin@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On 05/22/2015 04:20 PM, Ralf Baechle wrote: > On Fri, May 22, 2015 at 11:37:34AM -0700, Leonid Yegoshin wrote: > >> On 05/22/2015 02:38 AM, Ralf Baechle wrote: >>> Just move the call to finish_arch_switch(). >> It might be a problem later, then a correct MSA partiton starts working. It >> should be tight to saving MSA registers in that case. >> >>> Your rewrite also dropped the if (cpu_has_msa) condition from >>> disable_msa() probably causing havoc on lots of CPUs which will likely not >>> decode the set bits of the MFC0/MTC0 instructions thus end up accessing >>> Config0. Ralf >> Right before this chunk of code there is a saving MSA registers. Does it >> causing a havoc or else? >> >> May I ask you to look into switch_to macro to figure out how "if >> (cpu_has_msa)" check works in this case? > Ah sorry I now see that your added code is not executed for all CPUs but > only those having MSA. So then it's safe. > > Still I don't stylistically like defining the register t4 in the middle > of the code. > > Below my suggested patch. It's advantage is that for non-MSA platforms > the call to disable_msa() will be removed entirely. > > Something like Paul's http://patchwork.linux-mips.org/patch/10111/ (assuming > it's correct and tested) seems like a full cleanup but it's way too > complex for 4.1 or the stable kernels. > > Ralf > > All 3 patches seems working (I tested), but if you don't like mine then I prefer Paul's patch more - it concentrates stuff more closely and removes some assembly stuff. Besides that, it introduces lose_fpu_inatomic() which is needed for me :) - Leonid. From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailapp01.imgtec.com ([195.59.15.196]:35805 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27006688AbbEWACxdvEF7 (ORCPT ); Sat, 23 May 2015 02:02:53 +0200 Message-ID: <555FC32A.4020308@imgtec.com> Date: Fri, 22 May 2015 17:00:42 -0700 From: Leonid Yegoshin MIME-Version: 1.0 Subject: Re: [PATCH 1/2] MIPS: MSA: bugfix - disable MSA during thread switch correctly References: <20150519211222.35859.52798.stgit@ubuntu-yegoshin> <20150519211351.35859.80332.stgit@ubuntu-yegoshin> <20150522093812.GH6941@linux-mips.org> <555F776E.3070904@imgtec.com> <20150522232019.GA10556@linux-mips.org> In-Reply-To: <20150522232019.GA10556@linux-mips.org> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: Ralf Baechle Cc: linux-mips@linux-mips.org, rusty@rustcorp.com.au, alexinbeijing@gmail.com, paul.burton@imgtec.com, david.daney@cavium.com, alex@alex-smith.me.uk, linux-kernel@vger.kernel.org, james.hogan@imgtec.com, markos.chandras@imgtec.com, macro@linux-mips.org, eunb.song@samsung.com, manuel.lauss@gmail.com, andreas.herrmann@caviumnetworks.com Message-ID: <20150523000042.gFN5f85Ke0Rffz2GPOqWvUGqHgIN7wa0x5c0XdfwhwE@z> On 05/22/2015 04:20 PM, Ralf Baechle wrote: > On Fri, May 22, 2015 at 11:37:34AM -0700, Leonid Yegoshin wrote: > >> On 05/22/2015 02:38 AM, Ralf Baechle wrote: >>> Just move the call to finish_arch_switch(). >> It might be a problem later, then a correct MSA partiton starts working. It >> should be tight to saving MSA registers in that case. >> >>> Your rewrite also dropped the if (cpu_has_msa) condition from >>> disable_msa() probably causing havoc on lots of CPUs which will likely not >>> decode the set bits of the MFC0/MTC0 instructions thus end up accessing >>> Config0. Ralf >> Right before this chunk of code there is a saving MSA registers. Does it >> causing a havoc or else? >> >> May I ask you to look into switch_to macro to figure out how "if >> (cpu_has_msa)" check works in this case? > Ah sorry I now see that your added code is not executed for all CPUs but > only those having MSA. So then it's safe. > > Still I don't stylistically like defining the register t4 in the middle > of the code. > > Below my suggested patch. It's advantage is that for non-MSA platforms > the call to disable_msa() will be removed entirely. > > Something like Paul's http://patchwork.linux-mips.org/patch/10111/ (assuming > it's correct and tested) seems like a full cleanup but it's way too > complex for 4.1 or the stable kernels. > > Ralf > > All 3 patches seems working (I tested), but if you don't like mine then I prefer Paul's patch more - it concentrates stuff more closely and removes some assembly stuff. Besides that, it introduces lose_fpu_inatomic() which is needed for me :) - Leonid.