From mboxrd@z Thu Jan  1 00:00:00 1970
From: Mikko Perttunen <mikko.perttunen-/1wQRMveznE@public.gmane.org>
Subject: Re: clk: tegra: Add closed loop support for the DFLL
Date: Sat, 23 May 2015 21:55:37 +0300
Message-ID: <5560CD29.5010206@kapsi.fi>
References: <20150523171549.GA27611@mwanda>
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To: Dan Carpenter <dan.carpenter-QHcLZuEGTsvQT0dZR+AlfA@public.gmane.org>, ttynkkynen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
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On 05/23/2015 08:15 PM, Dan Carpenter wrote:
> Hello Tuomas Tynkkynen,
>
> The patch 435874b0fdf4: "clk: tegra: Add closed loop support for the
> DFLL" from May 13, 2015, leads to the following static checker
> warning:
>
> 	drivers/clk/tegra/clk-dfll.c:1448 dfll_build_i2c_lut()
> 	warn: unsigned 'td->i2c_lut[0]' is never less than zero.
>
> drivers/clk/tegra/clk-dfll.c
>    1446          v = td->soc->min_millivolts * 1000;
>    1447          td->i2c_lut[0] = find_vdd_map_entry_exact(td, v);
>    1448          if (td->i2c_lut[0] < 0)
>                      ^^^^^^^^^^^^^^^^^^
> Never true.
>
>    1449                  goto out;
>    1450
>
> regards,
> dan carpenter

Thanks for checking; for now, this shouldn't cause any problems. I will 
post a patch on monday.

Cheers,
Mikko.