diff for duplicates of <556283D5.4030901@huawei.com>

diff --git a/a/1.txt b/N1/1.txt
index 726c47d..a66aa6f 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -106,7 +106,7 @@ OK
 > Well, I certainly wouldn't rule anything out.
 > 
 >> But now, this patch only support SMMU_IDR1.SIDSIZE <= 16. Suppose
->> SMMU_IDR1.SIDSIZE = 25，Lv2 table size at 4K, then Lv1 table need 2^(25 -
+>> SMMU_IDR1.SIDSIZE = 25?Lv2 table size at 4K, then Lv1 table need 2^(25 -
 >> 6 + 3) = 2^22 = 4M. If we pre-allocated all Lv2 table, we need 2^25 * 64 =
 >> 2^31 = 2G, that's too big. So we must only allocate Lv2 table when we
 >> needed.
@@ -150,17 +150,11 @@ OK. Will you support non-pci devices in patch version 2?
 >> if (SMMU_IDR0.Hyp)
 >>         execute command CMDQ_OP_TLBI_EL2_ALL
 >>
->> When SMMU_IDR0.Hyp=’0’, this command causes CERROR_ILL
+>> When SMMU_IDR0.Hyp=?0?, this command causes CERROR_ILL
 > 
 > Well spotted, thanks!
 > 
 > Will
 > 
 > .
-> 
-
-
-_______________________________________________
-iommu mailing list
-iommu@lists.linux-foundation.org
-https://lists.linuxfoundation.org/mailman/listinfo/iommu
+>
diff --git a/a/content_digest b/N1/content_digest
index 84741f0..9647aec 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -4,17 +4,10 @@
  "ref\020150512165500.GE2062@arm.com\0"
  "ref\055530C4F.5000605@huawei.com\0"
  "ref\020150521112555.GH21920@arm.com\0"
- "ref\020150521112555.GH21920-5wv7dgnIgG8@public.gmane.org\0"
- "From\0leizhen <thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>\0"
- "Subject\0Re: [PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices\0"
+ "From\0thunder.leizhen@huawei.com (leizhen)\0"
+ "Subject\0[PATCH 2/3] iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices\0"
  "Date\0Mon, 25 May 2015 10:07:17 +0800\0"
- "To\0Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\0"
- "Cc\0huxinwei-hv44wF8Li93QT0dZR+AlfA@public.gmane.org <huxinwei-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>"
-  iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>
-  Sanil kumar <sanil.kumar-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
-  Gaojianbo <gaojianbo-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
-  Dingtianhong <dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
- " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "On 2015/5/21 19:25, Will Deacon wrote:\n"
@@ -125,7 +118,7 @@
  "> Well, I certainly wouldn't rule anything out.\n"
  "> \n"
  ">> But now, this patch only support SMMU_IDR1.SIDSIZE <= 16. Suppose\n"
- ">> SMMU_IDR1.SIDSIZE = 25\357\274\214Lv2 table size at 4K, then Lv1 table need 2^(25 -\n"
+ ">> SMMU_IDR1.SIDSIZE = 25?Lv2 table size at 4K, then Lv1 table need 2^(25 -\n"
  ">> 6 + 3) = 2^22 = 4M. If we pre-allocated all Lv2 table, we need 2^25 * 64 =\n"
  ">> 2^31 = 2G, that's too big. So we must only allocate Lv2 table when we\n"
  ">> needed.\n"
@@ -169,19 +162,13 @@
  ">> if (SMMU_IDR0.Hyp)\n"
  ">>         execute command CMDQ_OP_TLBI_EL2_ALL\n"
  ">>\n"
- ">> When SMMU_IDR0.Hyp=\342\200\2310\342\200\231, this command causes CERROR_ILL\n"
+ ">> When SMMU_IDR0.Hyp=?0?, this command causes CERROR_ILL\n"
  "> \n"
  "> Well spotted, thanks!\n"
  "> \n"
  "> Will\n"
  "> \n"
  "> .\n"
- "> \n"
- "\n"
- "\n"
- "_______________________________________________\n"
- "iommu mailing list\n"
- "iommu@lists.linux-foundation.org\n"
- https://lists.linuxfoundation.org/mailman/listinfo/iommu
+ >
 
-468806fd59dcd7edb666f00c0a771a5bc18a5525e5be44a16f4cce5586fb5db0
+8d4cdc23256d9ca4a7c09aeae0bcf31ded105fdc26b4365fc737dbda790c2503
