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From: Richard Henderson <rth@twiddle.net>
To: Peter Maydell <peter.maydell@linaro.org>,
	Yongbok Kim <yongbok.kim@imgtec.com>
Cc: "Leon Alrae" <leon.alrae@imgtec.com>,
	"QEMU Developers" <qemu-devel@nongnu.org>,
	"Andreas Färber" <afaerber@suse.de>
Subject: Re: [Qemu-devel] [PATCH v5 2/3] softmmu: Add probe_write()
Date: Tue, 26 May 2015 10:33:31 -0700	[thread overview]
Message-ID: <5564AE6B.4070406@twiddle.net> (raw)
In-Reply-To: <CAFEAcA-u7yoAv=23isSsEWwd6D9hAGJZTho-gCh+cQrHJA0SKw@mail.gmail.com>

On 05/26/2015 09:53 AM, Peter Maydell wrote:
> On 26 May 2015 at 17:49, Yongbok Kim <yongbok.kim@imgtec.com> wrote:
>> Add probe_write() forces a tlb_fill if the specified guest virtual
>> index isn't in the TCG softmmu TLB.
> 
> Surely the point is not to fill the TLB but to raise an
> exception if the address is not writable?
> 
>> +#if DATA_SIZE == 1
>> +/*
>> + * Force a tlb_fill if the specified guest virtual index isn't in the TCG
>> + * softmmu TLB.
>> + */
>> +void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
>> +                 uintptr_t retaddr)
>> +{
>> +    int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
>> +    target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
>> +
>> +    if ((addr & TARGET_PAGE_MASK)
>> +        != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
>> +        /* TLB entry is for a different page */
>> +        if (!VICTIM_TLB_HIT(addr_write)) {
>> +            tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
>> +        }
>> +    }
>> +}
>> +#endif
>>  #endif /* !defined(SOFTMMU_CODE_ACCESS) */
> 
> I think this code does what you want, but the comments are
> rather misleading...

Indeed.  The fact that the TLB gets loaded is merely a happy side-effect.


r~

  reply	other threads:[~2015-05-26 17:34 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-26 16:49 [Qemu-devel] [PATCH v5 0/3] target-mips: Add support for misaligned accesses Yongbok Kim
2015-05-26 16:49 ` [Qemu-devel] [PATCH v5 1/3] target-mips: Misaligned memory accesses for R6 Yongbok Kim
2015-05-26 16:49 ` [Qemu-devel] [PATCH v5 2/3] softmmu: Add probe_write() Yongbok Kim
2015-05-26 16:53   ` Peter Maydell
2015-05-26 17:33     ` Richard Henderson [this message]
2015-05-27  9:17       ` Yongbok Kim
2015-05-26 16:58   ` Andreas Färber
2015-05-26 17:16     ` Paolo Bonzini
2015-05-26 17:19     ` Peter Crosthwaite
2015-05-26 16:49 ` [Qemu-devel] [PATCH v5 3/3] target-mips: Misaligned memory accesses for MSA Yongbok Kim

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