From mboxrd@z Thu Jan  1 00:00:00 1970
From: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Subject: Re: [PATCH v22 02/14] x86/VPMU: Add public xenpmu.h
Date: Wed, 27 May 2015 11:18:21 -0400
Message-ID: <5565E03D.30009@oracle.com>
References: <1432231048-24880-1-git-send-email-boris.ostrovsky@oracle.com>
	<1432231048-24880-3-git-send-email-boris.ostrovsky@oracle.com>
	<5564B7C2020000780007DFF5@mail.emea.novell.com>
	<5564B255.10306@oracle.com>
	<5565D47F020000780007E30F@mail.emea.novell.com>
	<5565CA5A.6080406@oracle.com>
	<5565F043020000780007E3D7@mail.emea.novell.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; Format="flowed"
Content-Transfer-Encoding: 7bit
Return-path: <xen-devel-bounces@lists.xen.org>
In-Reply-To: <5565F043020000780007E3D7@mail.emea.novell.com>
List-Unsubscribe: <http://lists.xen.org/cgi-bin/mailman/options/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=unsubscribe>
List-Post: <mailto:xen-devel@lists.xen.org>
List-Help: <mailto:xen-devel-request@lists.xen.org?subject=help>
List-Subscribe: <http://lists.xen.org/cgi-bin/mailman/listinfo/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=subscribe>
Sender: xen-devel-bounces@lists.xen.org
Errors-To: xen-devel-bounces@lists.xen.org
To: Jan Beulich <JBeulich@suse.com>
Cc: kevin.tian@intel.com, suravee.suthikulpanit@amd.com, andrew.cooper3@citrix.com, tim@xen.org, dietmar.hahn@ts.fujitsu.com, xen-devel@lists.xen.org, Aravind.Gopalakrishnan@amd.com, jun.nakajima@intel.com, dgdegra@tycho.nsa.gov
List-Id: xen-devel@lists.xenproject.org

On 05/27/2015 10:26 AM, Jan Beulich wrote:
>>>> On 27.05.15 at 15:44, <boris.ostrovsky@oracle.com> wrote:
>> Sorry, I meant amd/intel members of the union below (I forgot we were
>> already in the arch header file):
>>
>> +    /*
>> +     * Vendor-specific PMU registers.
>> +     * RW for both hypervisor and guest.
>> +     * Guest's updates to this field are verified and then loaded by the
>> +     * hypervisor into hardware during XENPMU_flush
>> +     */
>> +    union {
>> +        struct xen_pmu_amd_ctxt amd;
>> +        struct xen_pmu_intel_ctxt intel;
>> +
>> +        /*
>> +         * Padding for contexts (fixed parts only, does not include MSR banks
>> +         * that are specified by offsets)
>> +         */
>> +#define XENPMU_CTXT_PAD_SZ  128
>> +        uint8_t pad[XENPMU_CTXT_PAD_SZ];
>> +    } c;
>> +};
>>
>> I think they are first used in patch 11 so I assume you also want me to
>> just keep the pad here (with a comment explaining why it is here) until
>> that patch.
> Ah, those ones I simply recalled having checked in the previous
> version already.
>

But should they they also not be defined until later patch, to be 
consistent with how lapic_lvtpc's definition is deferred?

-boris