From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH V4 2/8] xen/arm: Add functions of mapping between vCPUID and virtual affinity Date: Fri, 29 May 2015 15:27:25 +0100 Message-ID: <5568774D.9000705@citrix.com> References: <1432808109-31466-1-git-send-email-cbz@baozis.org> <1432808109-31466-3-git-send-email-cbz@baozis.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YyLGa-0004KN-8y for xen-devel@lists.xenproject.org; Fri, 29 May 2015 14:28:08 +0000 In-Reply-To: <1432808109-31466-3-git-send-email-cbz@baozis.org> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Chen Baozi , xen-devel@lists.xenproject.org Cc: Julien Grall , Chen Baozi , Ian Campbell List-Id: xen-devel@lists.xenproject.org Hi Chen, On 28/05/15 11:15, Chen Baozi wrote: > From: Chen Baozi > > GICv3 restricts that the maximum number of CPUs in affinity 0 (one > cluster) is 16. That is to say the upper 4 bits of affinity 0 is unused. > Current implementation considers that AFF0 is equal to vCPUID, which > makes all vCPUs in one cluster, limiting its number to 16. If we would > like to support more than 16 number of vCPU in one guest, we need to > make use of AFF1. Considering the unused upper 4 bits, we need to create > a pair of functions mapping the vCPUID and virtual affinity. > > Signed-off-by: Chen Baozi > --- > xen/include/asm-arm/domain.h | 36 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h > index 75b17af..603a20b 100644 > --- a/xen/include/asm-arm/domain.h > +++ b/xen/include/asm-arm/domain.h > @@ -266,6 +266,42 @@ static inline unsigned int domain_max_vcpus(const struct domain *d) > return MAX_VIRT_CPUS; > } > > +/* > + * Due to the restriction of GICv3, the number of vCPUs in AFF0 is > + * limited to 16, thus only the first 4 bits of AFF0 are legal. We will > + * use the first 2 affinity levels here, expanding the number of vCPU up > + * to 4096 (16*256), which is more than 128 PEs that GIC-500 supports. > + * > + * Since we don't save information of vCPU's topology (affinity) in > + * vMPIDR at the moment, we map the vcpuid to the vMPIDR linearly. > + * > + * XXX: We may have multi-threading or virtual cluster information in > + * the future. > + */ > +static inline unsigned int vaffinity_to_vcpuid(register_t vaff) > +{ > + unsigned int vcpuid; > + > + vaff &= MPIDR_HWID_MASK; > + > + vcpuid = MPIDR_AFFINITY_LEVEL(vaff, 0); > + vcpuid |= MPIDR_AFFINITY_LEVEL(vaff, 1) << 4; > + > + return vcpuid; > +} > + > +static inline register_t vcpuid_to_vaffinity(unsigned int vcpuid) > +{ > + register_t vaff; > + > + BUILD_BUG_ON(!(MAX_VIRT_CPUS < ((1 << 12)))); Can you add a small comment to explain the 1 << 12? I.e we only support AFF0 (4 bits) and AFF1 (8 bits). Other than that this patch looks good to me. Regards, -- Julien Grall