From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH V5 06/10] tools/libxl: Set 'reg' of cpu node equal to MPIDR affinity for domU Date: Sun, 31 May 2015 14:16:20 +0100 Message-ID: <556B09A4.1050204@citrix.com> References: <1432984051-10838-1-git-send-email-cbz@baozis.org> <1432984051-10838-7-git-send-email-cbz@baozis.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Yz36H-0004sl-Kk for xen-devel@lists.xenproject.org; Sun, 31 May 2015 13:16:25 +0000 In-Reply-To: <1432984051-10838-7-git-send-email-cbz@baozis.org> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Chen Baozi , xen-devel@lists.xenproject.org Cc: Julien Grall , Chen Baozi , Ian Campbell List-Id: xen-devel@lists.xenproject.org Hi Chen, On 30/05/2015 12:07, Chen Baozi wrote: > From: Chen Baozi > > According to ARM CPUs bindings, the reg field should match the MPIDR's > affinity bits. We will use AFF0 and AFF1 when constructing the reg value > of the guest at the moment, for it is enough for the current max vcpu > number. > > Signed-off-by: Chen Baozi > --- > tools/libxl/libxl_arm.c | 14 ++++++++++++-- > 1 file changed, 12 insertions(+), 2 deletions(-) > > diff --git a/tools/libxl/libxl_arm.c b/tools/libxl/libxl_arm.c > index c5088c4..8aa4815 100644 > --- a/tools/libxl/libxl_arm.c > +++ b/tools/libxl/libxl_arm.c > @@ -272,6 +272,7 @@ static int make_cpus_node(libxl__gc *gc, void *fdt, int nr_cpus, > const struct arch_info *ainfo) > { > int res, i; > + uint64_t mpidr_aff; > > res = fdt_begin_node(fdt, "cpus"); > if (res) return res; > @@ -283,7 +284,16 @@ static int make_cpus_node(libxl__gc *gc, void *fdt, int nr_cpus, > if (res) return res; > > for (i = 0; i < nr_cpus; i++) { > - const char *name = GCSPRINTF("cpu@%d", i); > + const char *name; > + > + /* > + * According to ARM CPUs bindings, the reg field should match > + * the MPIDR's affinity bits. We will use AFF0 and AFF1 when > + * constructing the reg value of the guest at the moment, for it > + * is enough for the current max vcpu number. > + */ > + mpidr_aff = (uint64_t)((i & 0x0f) | (((i >> 4) & 0xff) << 8)); The cast is not necessary. Other than that: Reviewed-by: Julien Grall Regards, -- Julien Grall