From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36631) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yziow-0003Rl-Kv for qemu-devel@nongnu.org; Tue, 02 Jun 2015 05:49:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yzios-000545-1d for qemu-devel@nongnu.org; Tue, 02 Jun 2015 05:49:18 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:23557) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yzior-00053e-Rs for qemu-devel@nongnu.org; Tue, 02 Jun 2015 05:49:13 -0400 Message-ID: <556D7C0F.3000509@imgtec.com> Date: Tue, 2 Jun 2015 10:49:03 +0100 From: Leon Alrae MIME-Version: 1.0 References: <1433157204-19708-1-git-send-email-yongbok.kim@imgtec.com> In-Reply-To: <1433157204-19708-1-git-send-email-yongbok.kim@imgtec.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v7 0/3] target-mips: Add support for misaligned accesses List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yongbok Kim , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, afaerber@suse.de, rth@twiddle.net On 01/06/2015 12:13, Yongbok Kim wrote: > This patch set adds support for misaligned memory accesses in MIPS architecture > Release 6 and MIPS SIMD Architecture. > > The behaviour, semantics, and architecture specifications of misaligned memory > accesses are described in: > MIPS Architecture For Programmers Volume I-A: Introduction to the MIPS64 > Architecture, Appendix B Misaligned Memory Accesses. > Available at http://www.imgtec.com/mips/architectures/mips64.asp > > Regards, > Yongbok > > v7: > * Rephrased comments (Peter) > * Reverted changes for LDPC/LWPC (Leon) > * Fixed cosmetic issues (Leon) > > v6: > * Rephrased comments (Peter) > > v5: > * Rewrote R6 patch to use new MO_UNALIN (Richard) > * Further cleanup to pass caculated address for MSA LD/ ST (Richard) > > v4: > * Removed the work-around per the recent TCG change for misaligned accesses > * Added probe_write() (Richard) > * Used helper_ret_*_mmu directly (Richard) > * Removed TLB checking for MSA LD (Richard) > * Removed unnecessary save_cpu_state() calls > > v3: > * Rewrote MSA patch > * Work-around is using byte-to-byte accesses and endianness corrections for > R5+MSA. (This replaces the misaligned flag from v2.) (Leon) > * Bug fixes (Leon) > * Separate helper functions for each data formats > > v2: > * Removed re-translation in the mips_cpu_do_unaligned_access() (Peter) > * Checks validity only if an access is spanning into two pages in MSA (Leon) > * Introduced misaligned flag to indicate MSA ld/st is ongoing, is used to > allow misaligned accesses in the mips_cpu_do_unaligned_access() callback. > This is crucial to support MSA misaligned accesses in Release 5 cores. > > Yongbok Kim (3): > target-mips: Misaligned memory accesses for R6 > softmmu: Add probe_write() > target-mips: Misaligned memory accesses for MSA > > include/exec/exec-all.h | 2 + > softmmu_template.h | 22 +++++++ > target-mips/helper.h | 10 +++- > target-mips/op_helper.c | 136 ++++++++++++++++++++++------------------- > target-mips/translate.c | 66 ++++++++++++++------- > target-mips/translate_init.c | 2 +- > 6 files changed, 150 insertions(+), 88 deletions(-) > The series looks good to me: Reviewed-by: Leon Alrae Thanks, Leon PS: I've just noticed that some of do_*() functions are unused now, so they should be removed. I'll do that while applying to mips-next.