diff for duplicates of <556E7024.2080807@huawei.com> diff --git a/a/1.txt b/N1/1.txt index cf9aea2..b949f44 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -14,12 +14,12 @@ On 2015/5/30 9:51, Bintian Wang wrote: > Also add dts file to support HiKey development board which > based on Hi6220 SoC. > -> Signed-off-by: Bintian Wang <bintian.wang@huawei.com> -> Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org> -> Reviewed-by: Yiping Xu <xuyiping@hisilicon.com> -> Tested-by: Will Deacon <will.deacon@arm.com> -> Tested-by: Tyler Baker <tyler.baker@linaro.org> -> Tested-by: Kevin Hilman <khilman@linaro.org> +> Signed-off-by: Bintian Wang <bintian.wang-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> +> Acked-by: Haojian Zhuang <haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +> Reviewed-by: Yiping Xu <xuyiping-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> +> Tested-by: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> +> Tested-by: Tyler Baker <tyler.baker-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> +> Tested-by: Kevin Hilman <khilman-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > --- > arch/arm64/boot/dts/Makefile | 1 + > arch/arm64/boot/dts/hisilicon/Makefile | 5 + @@ -85,7 +85,7 @@ On 2015/5/30 9:51, Bintian Wang wrote: > + stdout-path = "serial0:115200n8"; > + }; > + -> + memory at 0 { +> + memory@0 { > + device_type = "memory"; > + reg = <0x0 0x0 0x0 0x40000000>; > + }; @@ -151,56 +151,56 @@ On 2015/5/30 9:51, Bintian Wang wrote: > + }; > + }; > + -> + cpu0: cpu at 0 { +> + cpu0: cpu@0 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + }; > + -> + cpu1: cpu at 1 { +> + cpu1: cpu@1 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + }; > + -> + cpu2: cpu at 2 { +> + cpu2: cpu@2 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x2>; > + enable-method = "psci"; > + }; > + -> + cpu3: cpu at 3 { +> + cpu3: cpu@3 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x3>; > + enable-method = "psci"; > + }; > + -> + cpu4: cpu at 100 { +> + cpu4: cpu@100 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + }; > + -> + cpu5: cpu at 101 { +> + cpu5: cpu@101 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x101>; > + enable-method = "psci"; > + }; > + -> + cpu6: cpu at 102 { +> + cpu6: cpu@102 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x102>; > + enable-method = "psci"; > + }; > + -> + cpu7: cpu at 103 { +> + cpu7: cpu@103 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x103>; @@ -208,7 +208,7 @@ On 2015/5/30 9:51, Bintian Wang wrote: > + }; > + }; > + -> + gic: interrupt-controller at f6801000 { +> + gic: interrupt-controller@f6801000 { > + compatible = "arm,gic-400"; > + reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ > + <0x0 0xf6802000 0 0x2000>, /* GICC */ @@ -259,7 +259,7 @@ On 2015/5/30 9:51, Bintian Wang wrote: > + #clock-cells = <1>; > + }; > + -> + uart0: uart at f8015000 { /* console */ +> + uart0: uart@f8015000 { /* console */ > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x0 0xf8015000 0x0 0x1000>; > + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; @@ -269,3 +269,8 @@ On 2015/5/30 9:51, Bintian Wang wrote: > + }; > +}; > + +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index bbad63c..87cf060 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,54 @@ "ref\01432950661-23060-1-git-send-email-bintian.wang@huawei.com\0" "ref\01432950661-23060-6-git-send-email-bintian.wang@huawei.com\0" - "From\0bintian.wang@huawei.com (Bintian)\0" - "Subject\0[PATCH v9 5/6] arm64: dts: Add dts files for Hisilicon Hi6220 SoC\0" + "ref\01432950661-23060-6-git-send-email-bintian.wang-hv44wF8Li93QT0dZR+AlfA@public.gmane.org\0" + "From\0Bintian <bintian.wang-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>\0" + "Subject\0Re: [PATCH v9 5/6] arm64: dts: Add dts files for Hisilicon Hi6220 SoC\0" "Date\0Wed, 3 Jun 2015 11:10:28 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0catalin.marinas-5wv7dgnIgG8@public.gmane.org" + will.deacon-5wv7dgnIgG8@public.gmane.org + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + pawel.moll-5wv7dgnIgG8@public.gmane.org + mark.rutland-5wv7dgnIgG8@public.gmane.org + ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org + galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org + khilman-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + rob.herring-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org + sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org + khilman-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + arnd-r2nGTMty4D4@public.gmane.org + " marc.zyngier-5wv7dgnIgG8@public.gmane.org\0" + "Cc\0Bintian Wang <bintian.wang-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>" + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + xuwei5-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org + jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org + yanhaifeng-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org + xuejiancheng-hv44wF8Li93QT0dZR+AlfA@public.gmane.org + sledge.yanwei-hv44wF8Li93QT0dZR+AlfA@public.gmane.org + tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org + linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org + guodong.xu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + jorge.ramirez-ortiz-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + tyler.baker-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + pebolle-IWqWACnzNjzz+pZb47iToQ@public.gmane.org + xuyiping-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org + wangbinghui-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org + zhenwei.wang-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org + victor.lixin-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org + puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org + dan.zhao-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org + huxinwei-hv44wF8Li93QT0dZR+AlfA@public.gmane.org + z.liuxinliang-hv44wF8Li93QT0dZR+AlfA@public.gmane.org + heyunlei-hv44wF8Li93QT0dZR+AlfA@public.gmane.org + kong.kongxinwei-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org + wangbintian-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org + w.f-hv44wF8Li93QT0dZR+AlfA@public.gmane.org + " liguozhu-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org\0" "\00:1\0" "b\0" "Hello Mark, Rob and other ARM64 DT maintainers,\n" @@ -22,12 +67,12 @@ "> Also add dts file to support HiKey development board which\n" "> based on Hi6220 SoC.\n" ">\n" - "> Signed-off-by: Bintian Wang <bintian.wang@huawei.com>\n" - "> Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>\n" - "> Reviewed-by: Yiping Xu <xuyiping@hisilicon.com>\n" - "> Tested-by: Will Deacon <will.deacon@arm.com>\n" - "> Tested-by: Tyler Baker <tyler.baker@linaro.org>\n" - "> Tested-by: Kevin Hilman <khilman@linaro.org>\n" + "> Signed-off-by: Bintian Wang <bintian.wang-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>\n" + "> Acked-by: Haojian Zhuang <haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\n" + "> Reviewed-by: Yiping Xu <xuyiping-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>\n" + "> Tested-by: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\n" + "> Tested-by: Tyler Baker <tyler.baker-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\n" + "> Tested-by: Kevin Hilman <khilman-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\n" "> ---\n" "> arch/arm64/boot/dts/Makefile | 1 +\n" "> arch/arm64/boot/dts/hisilicon/Makefile | 5 +\n" @@ -93,7 +138,7 @@ "> +\t\tstdout-path = \"serial0:115200n8\";\n" "> +\t};\n" "> +\n" - "> +\tmemory at 0 {\n" + "> +\tmemory@0 {\n" "> +\t\tdevice_type = \"memory\";\n" "> +\t\treg = <0x0 0x0 0x0 0x40000000>;\n" "> +\t};\n" @@ -159,56 +204,56 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu0: cpu at 0 {\n" + "> +\t\tcpu0: cpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x0>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu1: cpu at 1 {\n" + "> +\t\tcpu1: cpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x1>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu2: cpu at 2 {\n" + "> +\t\tcpu2: cpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x2>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu3: cpu at 3 {\n" + "> +\t\tcpu3: cpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x3>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu4: cpu at 100 {\n" + "> +\t\tcpu4: cpu@100 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x100>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu5: cpu at 101 {\n" + "> +\t\tcpu5: cpu@101 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x101>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu6: cpu at 102 {\n" + "> +\t\tcpu6: cpu@102 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x102>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu7: cpu at 103 {\n" + "> +\t\tcpu7: cpu@103 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x103>;\n" @@ -216,7 +261,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at f6801000 {\n" + "> +\tgic: interrupt-controller@f6801000 {\n" "> +\t\tcompatible = \"arm,gic-400\";\n" "> +\t\treg = <0x0 0xf6801000 0 0x1000>, /* GICD */\n" "> +\t\t <0x0 0xf6802000 0 0x2000>, /* GICC */\n" @@ -267,7 +312,7 @@ "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart0: uart at f8015000 {\t/* console */\n" + "> +\t\tuart0: uart@f8015000 {\t/* console */\n" "> +\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "> +\t\t\treg = <0x0 0xf8015000 0x0 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -276,6 +321,11 @@ "> +\t\t};\n" "> +\t};\n" "> +};\n" - > + ">\n" + "\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -a27f16b88893a08331b9b50b2747ddc2436290ece4283b70b1be06c919ab452b +292676d954b8d0fe4aebd561cbdbfec7da73cc6c5dbb577aee5b38e9429dc221
diff --git a/a/1.txt b/N2/1.txt index cf9aea2..e1a1e65 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -85,7 +85,7 @@ On 2015/5/30 9:51, Bintian Wang wrote: > + stdout-path = "serial0:115200n8"; > + }; > + -> + memory at 0 { +> + memory@0 { > + device_type = "memory"; > + reg = <0x0 0x0 0x0 0x40000000>; > + }; @@ -151,56 +151,56 @@ On 2015/5/30 9:51, Bintian Wang wrote: > + }; > + }; > + -> + cpu0: cpu at 0 { +> + cpu0: cpu@0 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + }; > + -> + cpu1: cpu at 1 { +> + cpu1: cpu@1 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + }; > + -> + cpu2: cpu at 2 { +> + cpu2: cpu@2 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x2>; > + enable-method = "psci"; > + }; > + -> + cpu3: cpu at 3 { +> + cpu3: cpu@3 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x3>; > + enable-method = "psci"; > + }; > + -> + cpu4: cpu at 100 { +> + cpu4: cpu@100 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + }; > + -> + cpu5: cpu at 101 { +> + cpu5: cpu@101 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x101>; > + enable-method = "psci"; > + }; > + -> + cpu6: cpu at 102 { +> + cpu6: cpu@102 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x102>; > + enable-method = "psci"; > + }; > + -> + cpu7: cpu at 103 { +> + cpu7: cpu@103 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x103>; @@ -208,7 +208,7 @@ On 2015/5/30 9:51, Bintian Wang wrote: > + }; > + }; > + -> + gic: interrupt-controller at f6801000 { +> + gic: interrupt-controller@f6801000 { > + compatible = "arm,gic-400"; > + reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ > + <0x0 0xf6802000 0 0x2000>, /* GICC */ @@ -259,7 +259,7 @@ On 2015/5/30 9:51, Bintian Wang wrote: > + #clock-cells = <1>; > + }; > + -> + uart0: uart at f8015000 { /* console */ +> + uart0: uart@f8015000 { /* console */ > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x0 0xf8015000 0x0 0x1000>; > + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; diff --git a/a/content_digest b/N2/content_digest index bbad63c..71e96c5 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,9 +1,53 @@ "ref\01432950661-23060-1-git-send-email-bintian.wang@huawei.com\0" "ref\01432950661-23060-6-git-send-email-bintian.wang@huawei.com\0" - "From\0bintian.wang@huawei.com (Bintian)\0" - "Subject\0[PATCH v9 5/6] arm64: dts: Add dts files for Hisilicon Hi6220 SoC\0" + "From\0Bintian <bintian.wang@huawei.com>\0" + "Subject\0Re: [PATCH v9 5/6] arm64: dts: Add dts files for Hisilicon Hi6220 SoC\0" "Date\0Wed, 3 Jun 2015 11:10:28 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0<catalin.marinas@arm.com>" + <will.deacon@arm.com> + <devicetree@vger.kernel.org> + <robh+dt@kernel.org> + <pawel.moll@arm.com> + <mark.rutland@arm.com> + <ijc+devicetree@hellion.org.uk> + <galak@codeaurora.org> + <khilman@linaro.org> + <mturquette@linaro.org> + <rob.herring@linaro.org> + <haojian.zhuang@linaro.org> + <olof@lixom.net> + <sboyd@codeaurora.org> + <khilman@kernel.org> + <arnd@arndb.de> + " <marc.zyngier@arm.com>\0" + "Cc\0Bintian Wang <bintian.wang@huawei.com>" + <linux-arm-kernel@lists.infradead.org> + <linux-kernel@vger.kernel.org> + <zhangfei.gao@linaro.org> + <xuwei5@hisilicon.com> + <jh80.chung@samsung.com> + <yanhaifeng@gmail.com> + <xuejiancheng@huawei.com> + <sledge.yanwei@huawei.com> + <tomeu.vizoso@collabora.com> + <linux@arm.linux.org.uk> + <guodong.xu@linaro.org> + <jorge.ramirez-ortiz@linaro.org> + <tyler.baker@linaro.org> + <pebolle@tiscali.nl> + <xuyiping@hisilicon.com> + <wangbinghui@hisilicon.com> + <zhenwei.wang@hisilicon.com> + <victor.lixin@hisilicon.com> + <puck.chen@hisilicon.com> + <dan.zhao@hisilicon.com> + <huxinwei@huawei.com> + <z.liuxinliang@huawei.com> + <heyunlei@huawei.com> + <kong.kongxinwei@hisilicon.com> + <wangbintian@gmail.com> + <w.f@huawei.com> + " <liguozhu@hisilicon.com>\0" "\00:1\0" "b\0" "Hello Mark, Rob and other ARM64 DT maintainers,\n" @@ -93,7 +137,7 @@ "> +\t\tstdout-path = \"serial0:115200n8\";\n" "> +\t};\n" "> +\n" - "> +\tmemory at 0 {\n" + "> +\tmemory@0 {\n" "> +\t\tdevice_type = \"memory\";\n" "> +\t\treg = <0x0 0x0 0x0 0x40000000>;\n" "> +\t};\n" @@ -159,56 +203,56 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu0: cpu at 0 {\n" + "> +\t\tcpu0: cpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x0>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu1: cpu at 1 {\n" + "> +\t\tcpu1: cpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x1>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu2: cpu at 2 {\n" + "> +\t\tcpu2: cpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x2>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu3: cpu at 3 {\n" + "> +\t\tcpu3: cpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x3>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu4: cpu at 100 {\n" + "> +\t\tcpu4: cpu@100 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x100>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu5: cpu at 101 {\n" + "> +\t\tcpu5: cpu@101 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x101>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu6: cpu at 102 {\n" + "> +\t\tcpu6: cpu@102 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x102>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu7: cpu at 103 {\n" + "> +\t\tcpu7: cpu@103 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x103>;\n" @@ -216,7 +260,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at f6801000 {\n" + "> +\tgic: interrupt-controller@f6801000 {\n" "> +\t\tcompatible = \"arm,gic-400\";\n" "> +\t\treg = <0x0 0xf6801000 0 0x1000>, /* GICD */\n" "> +\t\t <0x0 0xf6802000 0 0x2000>, /* GICC */\n" @@ -267,7 +311,7 @@ "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart0: uart at f8015000 {\t/* console */\n" + "> +\t\tuart0: uart@f8015000 {\t/* console */\n" "> +\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "> +\t\t\treg = <0x0 0xf8015000 0x0 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -278,4 +322,4 @@ "> +};\n" > -a27f16b88893a08331b9b50b2747ddc2436290ece4283b70b1be06c919ab452b +7e634b1bfea636c49270d2e042c108f0c7ec767fd388c66a05221a3bed3d5740
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