From: Leon Alrae <leon.alrae@imgtec.com>
To: Aurelien Jarno <aurelien@aurel32.net>
Cc: james.hogan@imgtec.com, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v2 1/7] target-mips: extend selected CP0 registers to 64-bits in MIPS32
Date: Fri, 5 Jun 2015 20:48:38 +0100 [thread overview]
Message-ID: <5571FD16.9000905@imgtec.com> (raw)
In-Reply-To: <20150604221406.GB6313@aurel32.net>
On 04/06/15 23:14, Aurelien Jarno wrote:
> If you change the size of these registers, you have to adjust the
> corresponding MFC0 function for MIPS32, as the tcg_gen_ld_tl() function
> will point to the wrong side of the field on big endian hosts.
I'll fix it, thanks for pointing this out.
Leon
next prev parent reply other threads:[~2015-06-05 19:48 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-03 9:32 [Qemu-devel] [PATCH v2 0/7] target-mips: add support for large physical addresses Leon Alrae
2015-06-03 9:32 ` [Qemu-devel] [PATCH v2 1/7] target-mips: extend selected CP0 registers to 64-bits in MIPS32 Leon Alrae
2015-06-04 22:14 ` Aurelien Jarno
2015-06-05 19:48 ` Leon Alrae [this message]
2015-06-03 9:32 ` [Qemu-devel] [PATCH v2 2/7] target-mips: support Page Frame Number Extension field Leon Alrae
2015-06-03 9:32 ` [Qemu-devel] [PATCH v2 3/7] target-mips: add CP0.PageGrain.ELPA support Leon Alrae
2015-06-03 9:32 ` [Qemu-devel] [PATCH v2 4/7] target-mips: add MTHC0 and MFHC0 instructions Leon Alrae
2015-06-03 9:32 ` [Qemu-devel] [PATCH v2 5/7] target-mips: correct MFC0 for CP0.EntryLo in MIPS64 Leon Alrae
2015-06-03 9:32 ` [Qemu-devel] [PATCH v2 6/7] target-mips: remove misleading comments in translate_init.c Leon Alrae
2015-06-03 9:32 ` [Qemu-devel] [PATCH v2 7/7] target-mips: enable XPA and LPA features Leon Alrae
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