From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.coquelin@st.com (Maxime Coquelin) Date: Tue, 9 Jun 2015 11:21:28 +0200 Subject: [PATCH 0/2] Add code to release secondary cores from holding pen. In-Reply-To: <1433780219-1245-1-git-send-email-peter.griffin@linaro.org> References: <1433780219-1245-1-git-send-email-peter.griffin@linaro.org> Message-ID: <5576B018.9050603@st.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Peter, On 06/08/2015 06:16 PM, Peter Griffin wrote: > I can't test this on a STiH418 platform, as I don't have one, but a similar > DT change will be required there as well. I'm not sure if u-boot uses > the same SBC DMEM offset by default or not. It should have changed. Could you also patch STiH418 DT to add cpu-release-addr in CPU 2 & 3 nodes? Thanks, Maxime From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Coquelin Subject: Re: [PATCH 0/2] Add code to release secondary cores from holding pen. Date: Tue, 9 Jun 2015 11:21:28 +0200 Message-ID: <5576B018.9050603@st.com> References: <1433780219-1245-1-git-send-email-peter.griffin@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1433780219-1245-1-git-send-email-peter.griffin@linaro.org> Sender: linux-kernel-owner@vger.kernel.org To: Peter Griffin , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, patrice.chotard@st.com, srinivas.kandagatla@gmail.com Cc: lee.jones@linaro.org, devicetree@vger.kernel.org List-Id: devicetree@vger.kernel.org Hi Peter, On 06/08/2015 06:16 PM, Peter Griffin wrote: > I can't test this on a STiH418 platform, as I don't have one, but a similar > DT change will be required there as well. I'm not sure if u-boot uses > the same SBC DMEM offset by default or not. It should have changed. Could you also patch STiH418 DT to add cpu-release-addr in CPU 2 & 3 nodes? Thanks, Maxime From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932798AbbFIJWI (ORCPT ); Tue, 9 Jun 2015 05:22:08 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:52173 "EHLO mx08-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753637AbbFIJV7 (ORCPT ); Tue, 9 Jun 2015 05:21:59 -0400 Message-ID: <5576B018.9050603@st.com> Date: Tue, 9 Jun 2015 11:21:28 +0200 From: Maxime Coquelin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Peter Griffin , , , , CC: , Subject: Re: [PATCH 0/2] Add code to release secondary cores from holding pen. References: <1433780219-1245-1-git-send-email-peter.griffin@linaro.org> In-Reply-To: <1433780219-1245-1-git-send-email-peter.griffin@linaro.org> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.201.23.80] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.14.151,1.0.33,0.0.0000 definitions=2015-06-09_08:2015-06-08,2015-06-09,1970-01-01 signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Peter, On 06/08/2015 06:16 PM, Peter Griffin wrote: > I can't test this on a STiH418 platform, as I don't have one, but a similar > DT change will be required there as well. I'm not sure if u-boot uses > the same SBC DMEM offset by default or not. It should have changed. Could you also patch STiH418 DT to add cpu-release-addr in CPU 2 & 3 nodes? Thanks, Maxime