From: Clint Taylor <clinton.a.taylor@intel.com>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/3] drm/i915: Align DSPSURF to 128k on VLV/CHV
Date: Thu, 11 Jun 2015 17:46:44 -0700 [thread overview]
Message-ID: <557A2BF4.8010506@intel.com> (raw)
In-Reply-To: <1434029476-958-2-git-send-email-ville.syrjala@linux.intel.com>
On 06/11/2015 06:31 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> VLV/CHV have problems with 4k aligned linear scanout buffers. The VLV
> docs got updated at some point to say that we need to align them to
> 128k, just like we do on gen4.
>
> So far I've seen the problem manifest when the stride is an odd multiple
> of 512 bytes, and the surface address meets the following pattern
> '(addr & 0xf000) == 0x1000' (also == 0x2000 is problematic on VLV). The
> result is a starcase effect (so some pages get dropped maybe?), with a
> few pages here and there clearly getting scannout out at the wrong position.
>
> I've not actually been able to reproduce this problem on gen4, so it's
> not clear of the issue is any way related to the 128k restrictions
> supposedly inherited from gen4. But let's hope the 128k alignment is
> sufficient to hide it all.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0ac213a..2221323 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2329,7 +2329,8 @@ static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
> {
> if (INTEL_INFO(dev_priv)->gen >= 9)
> return 256 * 1024;
> - else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv))
> + else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
> + IS_VALLEYVIEW(dev_priv))
> return 128 * 1024;
> else if (INTEL_INFO(dev_priv)->gen >= 4)
> return 4 * 1024;
>
Fairly straight forward now that we know VLV and CHV require the 128k
alignment.
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
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next prev parent reply other threads:[~2015-06-12 0:49 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-11 13:31 [PATCH 1/3] drm/i915: Actually respect DSPSURF alignment restrictions ville.syrjala
2015-06-11 13:31 ` [PATCH 2/3] drm/i915: Align DSPSURF to 128k on VLV/CHV ville.syrjala
2015-06-12 0:46 ` Clint Taylor [this message]
2015-06-12 4:47 ` Arun R Murthy
2015-06-11 13:31 ` [PATCH 3/3] drm/i915: Drop the 64k linear scanout alignment on gen2/3 ville.syrjala
2015-06-11 13:52 ` Chris Wilson
2015-06-14 23:18 ` shuang.he
2015-06-11 13:51 ` [PATCH 1/3] drm/i915: Actually respect DSPSURF alignment restrictions Chris Wilson
2015-06-12 10:50 ` Ville Syrjälä
2015-06-15 16:04 ` Daniel Vetter
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