From: Boris Ostrovsky <boris.ostrovsky@oracle.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: kevin.tian@intel.com, suravee.suthikulpanit@amd.com,
andrew.cooper3@citrix.com, tim@xen.org,
dietmar.hahn@ts.fujitsu.com, xen-devel@lists.xen.org,
Aravind.Gopalakrishnan@amd.com, jun.nakajima@intel.com,
dgdegra@tycho.nsa.gov
Subject: Re: [PATCH v24 08/15] x86/VPMU: When handling MSR accesses, leave fault injection to callers
Date: Mon, 15 Jun 2015 12:23:05 -0400 [thread overview]
Message-ID: <557EFBE9.40100@oracle.com> (raw)
In-Reply-To: <557F06020200007800084FDC@mail.emea.novell.com>
On 06/15/2015 11:06 AM, Jan Beulich wrote:
>>>> On 10.06.15 at 17:04, <boris.ostrovsky@oracle.com> wrote:
>> --- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
>> +++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
>> @@ -454,36 +454,41 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
>> IA32_DEBUGCTLMSR_BTS_OFF_USR;
>> if ( !(msr_content & ~supported) &&
>> vpmu_is_set(vpmu, VPMU_CPU_HAS_BTS) )
>> - return 1;
>> + return 0;
>> if ( (msr_content & supported) &&
>> !vpmu_is_set(vpmu, VPMU_CPU_HAS_BTS) )
>> printk(XENLOG_G_WARNING
>> "%pv: Debug Store unsupported on this CPU\n",
>> current);
>> }
>> - return 0;
>> + return -EINVAL;
>> }
>>
>> ASSERT(!supported);
>>
>> + if ( type == MSR_TYPE_COUNTER &&
>> + (msr_content &
>> + ~((1ull << core2_get_bitwidth_fix_count()) - 1)) )
>> + /* Writing unsupported bits to a fixed counter */
>> + return -EINVAL;
>> +
>> core2_vpmu_cxt = vpmu->context;
>> enabled_cntrs = vpmu->priv_context;
>> switch ( msr )
>> {
>> case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
>> core2_vpmu_cxt->global_status &= ~msr_content;
>> - return 1;
>> + return 0;
>> case MSR_CORE_PERF_GLOBAL_STATUS:
>> gdprintk(XENLOG_INFO, "Can not write readonly MSR: "
>> "MSR_PERF_GLOBAL_STATUS(0x38E)!\n");
>> - hvm_inject_hw_exception(TRAP_gp_fault, 0);
>> - return 1;
>> + return -EINVAL;
> Is it intentional that you convert a success to a failure here? If so,
> this should be mentioned (with reason) in the commit message. If
> not, this should be adjusted to there's no behavioral change here.
Yes, this is intentional. Until now return value indicated whether
access was to a PMU register. This worked for HVM guests since they can
do hvm_inject_trap() at any time. For PV guests we are called from
emulate_privileged_op() and we need to know whether access was
successful or not. This way emulate_privileged_op() will take care of
fault injection by returning 0.
-boris
next prev parent reply other threads:[~2015-06-15 16:23 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-10 15:04 [PATCH v24 00/15] x86/PMU: Xen PMU PV(H) support Boris Ostrovsky
2015-06-10 15:04 ` [PATCH v24 01/15] common/symbols: Export hypervisor symbols to privileged guest Boris Ostrovsky
2015-06-10 15:04 ` [PATCH v24 02/15] x86/VPMU: Add public xenpmu.h Boris Ostrovsky
2015-06-15 14:59 ` Jan Beulich
2015-06-10 15:04 ` [PATCH v24 03/15] x86/VPMU: Make vpmu not HVM-specific Boris Ostrovsky
2015-06-10 15:04 ` [PATCH v24 04/15] x86/VPMU: Interface for setting PMU mode and flags Boris Ostrovsky
2015-06-11 8:17 ` Tian, Kevin
2015-06-11 14:54 ` Boris Ostrovsky
2015-06-11 15:04 ` Jan Beulich
2015-06-11 15:14 ` Boris Ostrovsky
2015-06-11 16:09 ` Jan Beulich
2015-06-12 3:23 ` Tian, Kevin
2015-06-12 13:58 ` Boris Ostrovsky
2015-06-10 15:04 ` [PATCH v24 05/15] x86/VPMU: Initialize VPMUs with __initcall Boris Ostrovsky
2015-06-10 15:04 ` [PATCH v24 06/15] x86/VPMU: Initialize PMU for PV(H) guests Boris Ostrovsky
2015-06-11 8:21 ` Tian, Kevin
2015-06-10 15:04 ` [PATCH v24 07/15] x86/VPMU: Save VPMU state for PV guests during context switch Boris Ostrovsky
2015-06-10 15:04 ` [PATCH v24 08/15] x86/VPMU: When handling MSR accesses, leave fault injection to callers Boris Ostrovsky
2015-06-15 15:06 ` Jan Beulich
2015-06-15 16:23 ` Boris Ostrovsky [this message]
2015-06-10 15:04 ` [PATCH v24 09/15] x86/VPMU: Add support for PMU register handling on PV guests Boris Ostrovsky
2015-06-10 15:04 ` [PATCH v24 10/15] x86/VPMU: Use pre-computed masks when checking validity of MSRs Boris Ostrovsky
2015-06-11 8:22 ` Tian, Kevin
2015-06-10 15:04 ` [PATCH v24 11/15] VPMU/AMD: Check MSR values before writing to hardware Boris Ostrovsky
2015-06-10 15:04 ` [PATCH v24 12/15] x86/VPMU: Handle PMU interrupts for PV(H) guests Boris Ostrovsky
2015-06-11 8:38 ` Tian, Kevin
2015-06-11 9:33 ` Jan Beulich
2015-06-11 9:36 ` Tian, Kevin
2015-06-15 15:50 ` Jan Beulich
2015-06-15 17:17 ` Boris Ostrovsky
2015-06-16 7:45 ` Jan Beulich
2015-06-16 14:14 ` Boris Ostrovsky
2015-06-10 15:04 ` [PATCH v24 13/15] x86/VPMU: Merge vpmu_rdmsr and vpmu_wrmsr Boris Ostrovsky
2015-06-10 15:04 ` [PATCH v24 14/15] x86/VPMU: Add privileged PMU mode Boris Ostrovsky
2015-06-10 15:04 ` [PATCH v24 15/15] x86/VPMU: Move VPMU files up from hvm/ directory Boris Ostrovsky
2015-06-11 8:39 ` Tian, Kevin
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