From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?B?Q2hyaXN0aWFuIEvDtm5pZw==?= Subject: Re: [PATCH 1/2] drm/radeon: compute ring fix hibernation (CI GPU family). Date: Fri, 19 Jun 2015 09:15:32 +0200 Message-ID: <5583C194.8060905@vodafone.de> References: <1434666697-6295-1-git-send-email-j.glisse@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: Received: from pegasos-out.vodafone.de (pegasos-out.vodafone.de [80.84.1.38]) by gabe.freedesktop.org (Postfix) with ESMTP id 8183E6E629 for ; Fri, 19 Jun 2015 00:15:39 -0700 (PDT) In-Reply-To: <1434666697-6295-1-git-send-email-j.glisse@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: j.glisse@gmail.com, dri-devel@lists.freedesktop.org Cc: =?UTF-8?B?SsOpcsO0bWUgR2xpc3Nl?= , stable@vger.kernel.org List-Id: dri-devel@lists.freedesktop.org T24gMTkuMDYuMjAxNSAwMDozMSwgai5nbGlzc2VAZ21haWwuY29tIHdyb3RlOgo+IEZyb206IErD qXLDtG1lIEdsaXNzZSA8amdsaXNzZUByZWRoYXQuY29tPgo+Cj4gSW4gb3JkZXIgZm9yIGhpYmVy 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KTsKPiAgIAkJcmRldi0+cmluZ1tDQVlNQU5fUklOR19UWVBFX0NQMV9JTkRFWF0ucmVhZHkgPSBm YWxzZTsKPiAgIAkJcmRldi0+cmluZ1tDQVlNQU5fUklOR19UWVBFX0NQMl9JTkRFWF0ucmVhZHkg PSBmYWxzZTsKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f CmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpo dHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from pegasos-out.vodafone.de ([80.84.1.38]:46556 "EHLO pegasos-out.vodafone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751178AbbFSHUw (ORCPT ); Fri, 19 Jun 2015 03:20:52 -0400 Message-ID: <5583C194.8060905@vodafone.de> Date: Fri, 19 Jun 2015 09:15:32 +0200 From: =?UTF-8?B?Q2hyaXN0aWFuIEvDtm5pZw==?= MIME-Version: 1.0 To: j.glisse@gmail.com, dri-devel@lists.freedesktop.org CC: =?UTF-8?B?SsOpcsO0bWUgR2xpc3Nl?= , stable@vger.kernel.org Subject: Re: [PATCH 1/2] drm/radeon: compute ring fix hibernation (CI GPU family). References: <1434666697-6295-1-git-send-email-j.glisse@gmail.com> In-Reply-To: <1434666697-6295-1-git-send-email-j.glisse@gmail.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: On 19.06.2015 00:31, j.glisse@gmail.com wrote: > From: Jérôme Glisse > > In order for hibernation to reliably work we need to cleanup more > thoroughly the compute ring. Hibernation is different from suspend > resume as when we resume from hibernation the hardware is first > fully initialize by regular kernel then freeze callback happens > (which correspond to a suspend inside the radeon kernel driver) > and turn off each of the block. It turns out we were not cleanly > shutting down the compute ring. This patch fix that. > > Hibernation and suspend to ram were tested (several times) on : > Bonaire > Hawaii > Mullins > Kaveri > Kabini > > Cc: stable@vger.kernel.org > Signed-off-by: Jérôme Glisse > --- > drivers/gpu/drm/radeon/cik.c | 55 ++++++++++++++++++++++++++++++++++++++++++ > 1 files changed, 55 insertions(+), 0 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c > index ba50f3c..d2576d4 100644 > --- a/drivers/gpu/drm/radeon/cik.c > +++ b/drivers/gpu/drm/radeon/cik.c > @@ -4592,6 +4592,61 @@ static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable) > if (enable) > WREG32(CP_MEC_CNTL, 0); > else { > + u32 tmp; > + int idx, j; > + > + /* > + * To make hibernation reliable we need to clear compute ring > + * configuration before halting the compute ring. > + */ > + mutex_lock(&rdev->srbm_mutex); > + > + idx = CAYMAN_RING_TYPE_CP1_INDEX; > + cik_srbm_select(rdev, rdev->ring[idx].me, > + rdev->ring[idx].pipe, > + rdev->ring[idx].queue, 0); > + /* Disable wptr polling. */ > + tmp = RREG32(CP_PQ_WPTR_POLL_CNTL); > + tmp &= ~WPTR_POLL_EN; > + WREG32(CP_PQ_WPTR_POLL_CNTL, tmp); > + /* Disable HQD. */ > + if (RREG32(CP_HQD_ACTIVE) & 1) { > + WREG32(CP_HQD_DEQUEUE_REQUEST, 1); > + for (j = 0; j < rdev->usec_timeout; j++) { > + if (!(RREG32(CP_HQD_ACTIVE) & 1)) > + break; > + udelay(1); > + } > + WREG32(CP_HQD_DEQUEUE_REQUEST, 0); > + WREG32(CP_HQD_PQ_RPTR, 0); > + WREG32(CP_HQD_PQ_WPTR, 0); > + } > + cik_srbm_select(rdev, 0, 0, 0, 0); Could you factor out this part into a function which just takes a radeon_ring* argument? Apart from that this patch and the other one looks good to me, Christian. > + > + idx = CAYMAN_RING_TYPE_CP2_INDEX; > + cik_srbm_select(rdev, rdev->ring[idx].me, > + rdev->ring[idx].pipe, > + rdev->ring[idx].queue, 0); > + /* Disable wptr polling. */ > + tmp = RREG32(CP_PQ_WPTR_POLL_CNTL); > + tmp &= ~WPTR_POLL_EN; > + WREG32(CP_PQ_WPTR_POLL_CNTL, tmp); > + /* Disable HQD. */ > + if (RREG32(CP_HQD_ACTIVE) & 1) { > + WREG32(CP_HQD_DEQUEUE_REQUEST, 1); > + for (j = 0; j < rdev->usec_timeout; j++) { > + if (!(RREG32(CP_HQD_ACTIVE) & 1)) > + break; > + udelay(1); > + } > + WREG32(CP_HQD_DEQUEUE_REQUEST, 0); > + WREG32(CP_HQD_PQ_RPTR, 0); > + WREG32(CP_HQD_PQ_WPTR, 0); > + } > + cik_srbm_select(rdev, 0, 0, 0, 0); > + > + mutex_unlock(&rdev->srbm_mutex); > + > WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT)); > rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; > rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;