From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45474) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5qwN-0002NA-B7 for qemu-devel@nongnu.org; Fri, 19 Jun 2015 03:42:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z5qwJ-0008FZ-5e for qemu-devel@nongnu.org; Fri, 19 Jun 2015 03:42:19 -0400 Received: from mx1.redhat.com ([209.132.183.28]:60040) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5qwJ-0008F2-0A for qemu-devel@nongnu.org; Fri, 19 Jun 2015 03:42:15 -0400 Message-ID: <5583C7D0.6050908@redhat.com> Date: Fri, 19 Jun 2015 09:42:08 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <1434642290-17610-1-git-send-email-fred.konrad@greensocs.com> <5BED6CA1-C0F5-4F08-A508-0DED044B5AEF@greensocs.com> <5583C538.6010707@redhat.com> <18093935-2D4D-43F3-90AA-48832146FB7B@greensocs.com> In-Reply-To: <18093935-2D4D-43F3-90AA-48832146FB7B@greensocs.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [RFC PATCH V3] Use atomic cmpxchg to atomically check the exclusive value in a STREX List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Mark Burton Cc: mttcg@greensocs.com, Peter Maydell , Alexander Graf , QEMU Developers , Guillaume Delbergue , =?UTF-8?B?QWxleCBCZQ==?= =?UTF-8?B?bm7DqWU=?= , =?UTF-8?B?S09OUkFEIEZyw6lkw6k=?= =?UTF-8?B?cmlj?= On 19/06/2015 09:40, Mark Burton wrote: >> On 19/06/2015 09:29, Mark Burton wrote: >>> Does anybody know if the current atomic_cmpxchg will support >>> 64 bit on a (normal) 32 bit x86, or do we need to special >>> case that with cmpxchg8b ? (I get the impression that it will >>> automatically use cmpxchg8b, but not cmpxchg16b - but I=E2=80=99m by >>> no means sure). >>=20 >> Both cmpxchg8b and cmpxchg16b are used, respectively on 32-bit >> and 64-bit x86. >=20 > Thanks Paolo, so we are OK for x86, but we would need to disable > multi-thread for other 32 bit hosts, and provide a correct > implementation for non multi-thread=E2=80=A6 But Alvise's implementation for example would work there. It is just this optimization (that is also not architecturally correct on ARM) that is problematic. Paolo > You dont happen to know of a > convenient macro we can use to test for =E2=80=9932 bit hosts that dont > support 64bit cmpxchg =E2=80=A6.=E2=80=99